Author: ranma
Date: Mon Nov 29 21:40:33 2010
New Revision: 6132
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6132
Log:
Tobias Diedrich wrote:
> Stefan Reinauer wrote:
> > The specified IO port is most likely wrong. As the comment mentions, the
> > SSDT is a good place for that. A preprocessor define used both in the
> > CPU init code and in the asl would solve the problem without an SSDT.
> > For some info on CPU SSDT creation on intel check out
> > src/cpu/intel/speedstep/acpi.c
>
> The IO port is ok (and I wrote the comment myself ;)):
> DEFAULT_PMBASE is 0xe400
> PCNTRL reg offset is 0x10
>
> Using the preprocessor will probably work too if iasl can do simple
> arithmetic (likely yes), I'll look into that.
BTW, my first idea was to use an acpi method that looks up pmbase in
the pci cfg space, but when I define a method like this:
Method(TEST, 2)
{
Return (Add(Arg0, Arg1))
}
I get:
|build/mainboard/asus/p2b/dsdt.ramstage.asl 9: Processor (CPU0,
|0x01, TEST(0xe400, 0x10), 0x06) {}
|Error 4096 - syntax error, unexpected PARSEOP_NAMESEG,
|expecting ')' ^
While using the builtin Add() directly works.
Signed-off-by: Tobias Diedrich <[email protected]>
Acked-by: Uwe Hermann <[email protected]>
Modified:
trunk/src/mainboard/asus/p2b/dsdt.asl
trunk/src/southbridge/intel/i82371eb/i82371eb.h
Modified: trunk/src/mainboard/asus/p2b/dsdt.asl
==============================================================================
--- trunk/src/mainboard/asus/p2b/dsdt.asl Mon Nov 29 12:56:39 2010
(r6131)
+++ trunk/src/mainboard/asus/p2b/dsdt.asl Mon Nov 29 21:40:33 2010
(r6132)
@@ -17,14 +17,17 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#include "southbridge/intel/i82371eb/i82371eb.h"
+
DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE ", "COREBOOT", 1)
{
/* Define the main processor.*/
Scope (\_PR)
{
- /* Looks like the P_CNT field can't be a method or name
- * and has to be hardcoded to 0xe410 or generated in SSDT */
- Processor (CPU0, 0x01, 0xe410, 0x06) {}
+ /* Looks like the P_CNT field can't be a name or method (except
+ * builtins like Add()) and has to be hardcoded or generated
+ * into SSDT */
+ Processor (CPU0, 0x01, Add(DEFAULT_PMBASE, PCNTRL), 0x06) {}
}
/* For now only define 2 power states:
Modified: trunk/src/southbridge/intel/i82371eb/i82371eb.h
==============================================================================
--- trunk/src/southbridge/intel/i82371eb/i82371eb.h Mon Nov 29 12:56:39
2010 (r6131)
+++ trunk/src/southbridge/intel/i82371eb/i82371eb.h Mon Nov 29 21:40:33
2010 (r6132)
@@ -23,6 +23,7 @@
#if !defined(ASSEMBLY)
#if !defined(__PRE_RAM__)
+#if !defined(__ACPI__) /* dsdt include */
#include <arch/io.h>
#include <device/device.h>
@@ -33,6 +34,7 @@
#endif
#endif
+#endif
/* If 'cond' is true this macro sets the bit(s) specified by 'bits' in the
* 'reg' variable, otherwise it clears those bits.
--
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