Stefan Reinauer wrote: > * Tobias Diedrich <[email protected]> [101128 11:43]: > > The IO port is ok (and I wrote the comment myself ;)): > > DEFAULT_PMBASE is 0xe400 > > PCNTRL reg offset is 0x10 > > Oh, I think that's even worse... ;) > > 1) DEFAULT_PMBASE must be lower than 0x1000 to avoid conflicts with the > resource allocator.
It's registered as a fixed resource in i82371eb_smbus.c (added by me in the acpi patch), so it shouldn't be a problem. > 2) The IO address in the Processor field should be configured > in the MSR PMG_IO_BASE_ADDR (0xe3). This is only for newer processors I think, I didn't see an this msr in the msr list for PIII processors. It's handled by the 440bx chipset acpi registers instead. -- Tobias PGP: http://8ef7ddba.uguu.de -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
