Hello,
This patch just turns on the ACPI resume support and adds needed cbmem.c. I
think this can be changed not to include it in some further patch.
Signed-off-by: Rudolf Marek <[email protected]>
I can test all patches next week, now they are just compile tested and based on
the preview patch.
Rudolf
Index: coreboot/src/mainboard/asrock/939a785gmh/Kconfig
===================================================================
--- coreboot.orig/src/mainboard/asrock/939a785gmh/Kconfig 2010-12-04 22:17:50.000000000 +0100
+++ coreboot/src/mainboard/asrock/939a785gmh/Kconfig 2010-12-04 22:18:14.000000000 +0100
@@ -11,6 +11,7 @@
select SOUTHBRIDGE_AMD_SB700
select SUPERIO_WINBOND_W83627DHG
select HAVE_ACPI_TABLES
+ select HAVE_ACPI_RESUME
select HAVE_MP_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MAINBOARD_RESOURCES
Index: coreboot/src/mainboard/asrock/939a785gmh/romstage.c
===================================================================
--- coreboot.orig/src/mainboard/asrock/939a785gmh/romstage.c 2010-12-04 22:17:51.000000000 +0100
+++ coreboot/src/mainboard/asrock/939a785gmh/romstage.c 2010-12-04 22:18:14.000000000 +0100
@@ -67,11 +67,22 @@
#include "lib/generic_sdram.c"
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
+
+
+// Now, this needs to be included because it relies on the symbol
+// __PRE_RAM__ being set during CAR stage (in order to compile the
+// BSS free versions of the functions). Either rewrite the code
+// to be always BSS free, or invent a flag that's better suited than
+// __PRE_RAM__ to determine whether we're in ram init stage (stage 1)
+//
+#include "lib/cbmem.c"
+
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
#include "cpu/amd/model_fxx/fidvid.c"
#include "northbridge/amd/amdk8/early_ht.c"
+
static void sio_init(void)
{
u8 reg;
--
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