I just want to add the serial port log file. It may help me to explain
the problem more clear.
Best,
Fengwei
-------- Original Message --------
Subject: Question on switching memory stick from dimm_mask 0x01 to
dimm_mask 0x10
Date: Fri, 10 Dec 2010 15:35:11 -0500
From: Fengwei Zhang <[email protected]>
To: [email protected]
Hi all,
For some reason, I need to switch my memory stick from dimm_mask 0x01 to
dimm_mask 0x10 on board asus m2v_mx_se.
I am using a 2G kingston DDR2 memory on board m2v_mx-se. If I put the
memory stick on board with dimm_mask 0x01. It could successfully boot
with coreboot.
But If I put the memory stick on board with dimm_mask 0x10. Booting
process would stop at pci_scan_bus() function after print out
post_code(0x24) on the serial port.
I also tried manufacture BIOS, it could successfully boot for both
dimm_mask 0x01 and 0x10.
Does anyone has this problem before? Is there anyway to fix this?
I would appreciate your precious comments!
Best,
Fengwei
coreboot-4.0-r6144M Fri Dec 10 13:06:41 EST 2010 starting...
now booting...
Enabling routing table for node 00 done.
Enabling UP settings
Disabling read/write/fill probes for UP... done.
coherent_ht_finalize
done
core0 started:
now booting... All core 0 started
started ap apicid:
SBLink=00
NC node|link=00
00entering optimize_link_incoherent_ht
sysinfo->link_pair_num=0x1
entering ht_optimize_link
pos=0x8a, unfiltered freq_cap=0x8075
pos=0x8a, filtered freq_cap=0x75
pos=0x6e, unfiltered freq_cap=0x75
pos=0x6e, filtered freq_cap=0x75
freq_cap1=0x75, freq_cap2=0x75
dev1 old_freq=0x0, freq=0x6, needs_reset=0x1
dev2 old_freq=0x0, freq=0x6, needs_reset=0x1
width_cap1=0x11, width_cap2=0x11
dev1 input ln_width1=0x4, ln_width2=0x4
dev1 input width=0x1
dev1 output ln_width1=0x4, ln_width2=0x4
dev1 input|output width=0x11
old dev1 input|output width=0x11
dev2 input|output width=0x11
old dev2 input|output width=0x11
after ht_optimize_link for link pair 0, reset_needed=0x1
after optimize_link_read_pointers_chain, reset_needed=0x1
01K8T890 found at LDT 00 Agreed on width: 01 CPU programmed to HT freq: 06 VIA
HT caps: 0075
01No config data specified, using default MAC!
ht reset -
soft reset
coreboot-4.0-r6144M Fri Dec 10 13:06:41 EST 2010 starting...
now booting...
Enabling routing table for node 00 done.
Enabling UP settings
Disabling read/write/fill probes for UP... done.
coherent_ht_finalize
done
core0 started:
now booting... All core 0 started
started ap apicid:
SBLink=00
NC node|link=00
00entering optimize_link_incoherent_ht
sysinfo->link_pair_num=0x1
entering ht_optimize_link
pos=0x8a, unfiltered freq_cap=0x8075
pos=0x8a, filtered freq_cap=0x75
pos=0x6e, unfiltered freq_cap=0x75
pos=0x6e, filtered freq_cap=0x75
freq_cap1=0x75, freq_cap2=0x75
dev1 old_freq=0x6, freq=0x6, needs_reset=0x0
dev2 old_freq=0x6, freq=0x6, needs_reset=0x0
width_cap1=0x11, width_cap2=0x11
dev1 input ln_width1=0x4, ln_width2=0x4
dev1 input width=0x1
dev1 output ln_width1=0x4, ln_width2=0x4
dev1 input|output width=0x11
old dev1 input|output width=0x11
dev2 input|output width=0x11
old dev2 input|output width=0x11
after ht_optimize_link for link pair 0, reset_needed=0x0
after optimize_link_read_pointers_chain, reset_needed=0x0
00K8T890 found at LDT 00 Agreed on width: 01 CPU programmed to HT freq: 06 VIA
HT caps: 0075
00after enable_fid_change
toggle LDTSTP#
done
Current fid_cur: 0x2, fid_max: 0xe
Requested fid_new: 0xe
FidVid table step fidvid: 0xe
toggle LDTSTP#
done
toggle LDTSTP#
done
Ram1.00
setting up CPU 00 northbridge registers
done.
Ram2.00
sdram_set_spd_registers: paramx :000ceed0
DIMM socket 0, channel 0 SPD device is 0x50
Device error
DIMM socket 0, channel 1 SPD device is 0x51
DIMM socket 1, channel 0 SPD device is 0x52
Device error
DIMM socket 1, channel 1 SPD device is 0x53
Device error
DIMM socket 2, channel 0 SPD device is 0x00
DIMM socket 2, channel 1 SPD device is 0x00
DIMM socket 3, channel 0 SPD device is 0x00
DIMM socket 3, channel 1 SPD device is 0x00
dimm_mask is: 10
Enable 64MuxMode & BurstLength32
Unbuffered
400MHz
400MHz
set_ecc spd_device: 0x51
Device error
Interleaved
RAM end at 0x00200000 kB
Ram3
IN TEST WAKEUP
00sysinfo->meminfo[0].dimm_mask: 10
Initializing memory: done
Setting variable MTRR 2, base: 0MB, range: 2048MB, type WB
DQS Training:RcvrEn:Pass1: 00
CTLRMaxDelay=17
done
DQS Training:DQSPos: 00
TrainDQSRdWrPos: buf_a:000ce9a0
TrainDQSPos: MutualCSPassW[48] :000ce878
TrainDQSPos: MutualCSPassW[48] :000ce878
TrainDQSPos: MutualCSPassW[48] :000ce878
TrainDQSPos: MutualCSPassW[48] :000ce888
done
DQS Training:RcvrEn:Pass2: 00
CTLRMaxDelay=3e
done
DQS SAVE NVRAM: c2000
Writing 111222 of size 4 to nvram pos: 0
Writing 0 of size 4 to nvram pos: 4
Writing 0 of size 4 to nvram pos: 8
Writing 0 of size 1 to nvram pos: 12
Writing 0 of size 4 to nvram pos: 13
Writing 2f2f2f2f of size 4 to nvram pos: 17
Writing 2f2f2f2f of size 4 to nvram pos: 21
Writing 0 of size 1 to nvram pos: 25
Writing 0 of size 1 to nvram pos: 26
Writing 0 of size 1 to nvram pos: 27
Writing 0 of size 1 to nvram pos: 28
Writing 0 of size 1 to nvram pos: 29
Writing 113222 of size 4 to nvram pos: 30
Writing 17161515 of size 4 to nvram pos: 34
Writing 15161616 of size 4 to nvram pos: 38
Writing 16 of size 1 to nvram pos: 42
Writing 202520 of size 4 to nvram pos: 43
Writing 17161616 of size 4 to nvram pos: 47
Writing 17181616 of size 4 to nvram pos: 51
Writing 16 of size 1 to nvram pos: 55
Writing 0 of size 1 to nvram pos: 56
Writing 0 of size 1 to nvram pos: 57
Writing 3e of size 1 to nvram pos: 58
Writing 0 of size 1 to nvram pos: 59
Writing 741080ab of size 4 to nvram pos: 60
DQS Training:tsc[00]=000000004f92a25d
DQS Training:tsc[01]=000000005181f300
DQS Training:tsc[02]=000000005181f309
DQS Training:tsc[03]=000000009b9fee94
DQS Training:tsc[04]=00000000b19ab90b
Ram4
v_esp=000cef18
testx = 5a5a5a5a
IN TEST WAKEUP
00Copying data from cache to RAM -- switching to use RAM as stack... Done
testx = ffff00000000000005a5a5a5a
Disabling cache as ram now
Clearing initial memory region: Done
Loading image.
Check CBFS header at fffffc6e
magic is 4f524243
Found CBFS header at fffffc6e
Check fallback/romstage
CBFS: follow chain: fff00000 + 38 + b9da + align -> fff0ba40
Check fallback/coreboot_ram
Stage: loading fallback/coreboot_ram @ 0x100000 (491520 bytes), entry @ 0x100000
Stage: done loading.
Jumping to image.
POST: 0x80
POST: 0x39
coreboot-4.0-r6144M Fri Dec 10 13:06:41 EST 2010 booting...
POST: 0x40
Enumerating buses...
Show all devs...Before device enumeration.
Root Device: enabled 1
APIC_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
PCI_DOMAIN: 0000: enabled 1
PCI: 00:18.0: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:0f.1: enabled 1
PCI: 00:11.0: enabled 1
I2C: 00:50: enabled 1
I2C: 00:51: enabled 1
I2C: 00:52: enabled 1
I2C: 00:53: enabled 1
PNP: 002e.0: enabled 1
PNP: 002e.1: enabled 1
PNP: 002e.2: enabled 0
PNP: 002e.3: enabled 1
PNP: 002e.4: enabled 1
PNP: 002e.5: enabled 0
PNP: 002e.6: enabled 0
PNP: 002e.7: enabled 0
PNP: 002e.8: enabled 0
PNP: 002e.9: enabled 0
PNP: 002e.a: enabled 0
PCI: 00:12.0: enabled 1
PCI: 00:13.0: enabled 1
PCI: 00:13.1: enabled 1
PCI: 00:18.1: enabled 1
PCI: 00:18.2: enabled 1
PCI: 00:18.3: enabled 1
Compare with tree...
Root Device: enabled 1
APIC_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
PCI_DOMAIN: 0000: enabled 1
PCI: 00:18.0: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:0f.1: enabled 1
PCI: 00:11.0: enabled 1
I2C: 00:50: enabled 1
I2C: 00:51: enabled 1
I2C: 00:52: enabled 1
I2C: 00:53: enabled 1
PNP: 002e.0: enabled 1
PNP: 002e.1: enabled 1
PNP: 002e.2: enabled 0
PNP: 002e.3: enabled 1
PNP: 002e.4: enabled 1
PNP: 002e.5: enabled 0
PNP: 002e.6: enabled 0
PNP: 002e.7: enabled 0
PNP: 002e.8: enabled 0
PNP: 002e.9: enabled 0
PNP: 002e.a: enabled 0
PCI: 00:12.0: enabled 1
PCI: 00:13.0: enabled 1
PCI: 00:13.1: enabled 1
PCI: 00:18.1: enabled 1
PCI: 00:18.2: enabled 1
PCI: 00:18.3: enabled 1
scan_static_bus for Root Device
APIC_CLUSTER: 0 enabled
PCI_DOMAIN: 0000 enabled
APIC_CLUSTER: 0 scanning...
PCI: 00:18.3 siblings=0
Found Rev E or Rev F later single core
CPU: APIC: 00 enabled
PCI_DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
POST: 0x24
--
coreboot mailing list: [email protected]
http://www.coreboot.org/mailman/listinfo/coreboot
