Author: stepan Date: Sat Dec 11 23:14:44 2010 New Revision: 6164 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6164
Log: factor out cpu power management base into a separate file. And fix a bug in model_1067x Signed-off-by: Stefan Reinauer <[email protected]> Acked-by: Stefan Reinauer <[email protected]> Added: trunk/src/include/cpu/intel/speedstep.h Modified: trunk/src/cpu/intel/model_1067x/model_1067x_init.c trunk/src/cpu/intel/model_106cx/model_106cx_init.c trunk/src/cpu/intel/model_6ex/model_6ex_init.c trunk/src/cpu/intel/model_6fx/model_6fx_init.c trunk/src/cpu/intel/speedstep/acpi.c Modified: trunk/src/cpu/intel/model_1067x/model_1067x_init.c ============================================================================== --- trunk/src/cpu/intel/model_1067x/model_1067x_init.c Sat Dec 11 23:12:32 2010 (r6163) +++ trunk/src/cpu/intel/model_1067x/model_1067x_init.c Sat Dec 11 23:14:44 2010 (r6164) @@ -28,6 +28,7 @@ #include <cpu/x86/msr.h> #include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> +#include <cpu/intel/speedstep.h> #include <cpu/intel/hyperthreading.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> @@ -98,8 +99,6 @@ #define PMG_IO_BASE_ADDR 0xe3 #define PMG_IO_CAPTURE_ADDR 0xe4 -#define PMB0_BASE 0x580 -#define PMB1_BASE 0x800 #define CST_RANGE 2 static void configure_c_states(void) { Modified: trunk/src/cpu/intel/model_106cx/model_106cx_init.c ============================================================================== --- trunk/src/cpu/intel/model_106cx/model_106cx_init.c Sat Dec 11 23:12:32 2010 (r6163) +++ trunk/src/cpu/intel/model_106cx/model_106cx_init.c Sat Dec 11 23:14:44 2010 (r6164) @@ -26,6 +26,7 @@ #include <cpu/x86/msr.h> #include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> +#include <cpu/intel/speedstep.h> #include <cpu/intel/hyperthreading.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> @@ -82,9 +83,7 @@ #define PMG_CST_CONFIG_CONTROL 0xe2 #define PMG_IO_BASE_ADDR 0xe3 #define PMG_IO_CAPTURE_ADDR 0xe4 -#define PMB0 0x510 /* analogous to P_BLK in cpu.asl */ -#define PMB1 0x0 /* IO port that triggers SMI once cores are in the same state. - See CSM Trigger, at PMG_CST_CONFIG_CONTROL[6:4] */ + #define HIGHEST_CLEVEL 3 static void configure_c_states(void) { Modified: trunk/src/cpu/intel/model_6ex/model_6ex_init.c ============================================================================== --- trunk/src/cpu/intel/model_6ex/model_6ex_init.c Sat Dec 11 23:12:32 2010 (r6163) +++ trunk/src/cpu/intel/model_6ex/model_6ex_init.c Sat Dec 11 23:14:44 2010 (r6164) @@ -29,6 +29,7 @@ #include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/intel/hyperthreading.h> +#include <cpu/intel/speedstep.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> #include <usbdebug.h> @@ -80,15 +81,6 @@ #define PMG_IO_BASE_ADDR 0xe3 #define PMG_IO_CAPTURE_ADDR 0xe4 -/* MWAIT coordination I/O base address. This must match - * the \_PR_.CPU0 PM base address. - */ -#define PMB0_BASE 0x510 - -/* PMB1: I/O port that triggers SMI once cores are in the same state. - * See CSM Trigger, at PMG_CST_CONFIG_CONTROL[6:4] - */ -#define PMB1_BASE 0x800 #define HIGHEST_CLEVEL 3 static void configure_c_states(void) { Modified: trunk/src/cpu/intel/model_6fx/model_6fx_init.c ============================================================================== --- trunk/src/cpu/intel/model_6fx/model_6fx_init.c Sat Dec 11 23:12:32 2010 (r6163) +++ trunk/src/cpu/intel/model_6fx/model_6fx_init.c Sat Dec 11 23:14:44 2010 (r6164) @@ -28,6 +28,7 @@ #include <cpu/x86/msr.h> #include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> +#include <cpu/intel/speedstep.h> #include <cpu/intel/hyperthreading.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> @@ -94,15 +95,6 @@ #define PMG_IO_BASE_ADDR 0xe3 #define PMG_IO_CAPTURE_ADDR 0xe4 -/* MWAIT coordination I/O base address. This must match - * the \_PR_.CPU0 PM base address. - */ -#define PMB0_BASE 0x510 - -/* PMB1: I/O port that triggers SMI once cores are in the same state. - * See CSM Trigger, at PMG_CST_CONFIG_CONTROL[6:4] - */ -#define PMB1_BASE 0x800 #define HIGHEST_CLEVEL 3 static void configure_c_states(void) { Modified: trunk/src/cpu/intel/speedstep/acpi.c ============================================================================== --- trunk/src/cpu/intel/speedstep/acpi.c Sat Dec 11 23:12:32 2010 (r6163) +++ trunk/src/cpu/intel/speedstep/acpi.c Sat Dec 11 23:14:44 2010 (r6164) @@ -26,6 +26,7 @@ #include <arch/cpu.h> #include <cpu/x86/msr.h> #include <cpu/intel/acpi.h> +#include <cpu/intel/speedstep.h> #include <device/device.h> // XXX: PSS table values for power consumption are for Merom only @@ -64,7 +65,7 @@ void generate_cpu_entries(void) { int len_pr, len_ps; - int coreID, cpuID, pcontrol_blk=0x510, plen=6; + int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6; msr_t msr; int totalcores = determine_total_number_of_cores(); int cores_per_package = (cpuid_ebx(1)>>16) & 0xff; Added: trunk/src/include/cpu/intel/speedstep.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/include/cpu/intel/speedstep.h Sat Dec 11 23:14:44 2010 (r6164) @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* MWAIT coordination I/O base address. This must match + * the \_PR_.CPU0 PM base address. + */ +#define PMB0_BASE 0x510 + +/* PMB1: I/O port that triggers SMI once cores are in the same state. + * See CSM Trigger, at PMG_CST_CONFIG_CONTROL[6:4] + */ +#define PMB1_BASE 0x800 + -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
