[coreboot] [commit] r6225 - in trunk/src: cpu/amd/model_gx2 southbridge/amd/cs5535 southbridge/amd/cs5536

[repository service]

Author: stepan
Date: Thu Dec 30 20:23:29 2010
New Revision: 6225
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6225

Log:
Remove duplicated GX2 processor IIOC mode setting on CS5535 southbridge code
and fix CIS mode comments.

Signed-off-by: Nils Jacobs <njaco...@hetnet.nl>
Acked-by: Stefan Reinauer <ste...@coreboot.org>

Modified:
   trunk/src/cpu/amd/model_gx2/cpureginit.c
   trunk/src/southbridge/amd/cs5535/early_setup.c
   trunk/src/southbridge/amd/cs5536/early_setup.c

Modified: trunk/src/cpu/amd/model_gx2/cpureginit.c
==============================================================================
--- trunk/src/cpu/amd/model_gx2/cpureginit.c    Thu Dec 30 20:21:08 2010        
(r6224)
+++ trunk/src/cpu/amd/model_gx2/cpureginit.c    Thu Dec 30 20:23:29 2010        
(r6225)
@@ -88,16 +88,13 @@
        msr.lo =  0x00000603C;
        wrmsr(msrnum, msr);
 
-/* Only do this if we are building for 5535 */
 /* FooGlue Setup */
-#if 1
-       /* Enable CIS mode B in FooGlue */
-       msrnum = MSR_FG + 0x10;
+       /* Set CS5535/CS5536 mode in FooGlue */
+       msrnum = FG_GIO_MSR_SEL;
        msr = rdmsr(msrnum);
        msr.lo &= ~3;
-       msr.lo |= 2;            /* ModeB */
+       msr.lo |= 2;            /* IIOC mode CS5535/CS5536 enable. (according 
to Jordan Crouse the databook is wrong bits 1:0 have to be 2 instead of 1) */
        wrmsr(msrnum, msr);
-#endif
 
 /* Disable DOT PLL. Graphics init will enable it if needed. */
        msrnum = GLCP_DOTPLL;

Modified: trunk/src/southbridge/amd/cs5535/early_setup.c
==============================================================================
--- trunk/src/southbridge/amd/cs5535/early_setup.c      Thu Dec 30 20:21:08 
2010        (r6224)
+++ trunk/src/southbridge/amd/cs5535/early_setup.c      Thu Dec 30 20:23:29 
2010        (r6225)
@@ -107,15 +107,11 @@
 {
        msr_t msr;
 
-       /* setup CPU interface serial to mode C on both sides */
+       /* Setup CPU serial SouthBridge interface to mode C. */
        msr = rdmsr(GLPCI_SB_CTRL);
        msr.lo &= ~0x18;
        msr.lo |= 0x10;
        wrmsr(GLPCI_SB_CTRL, msr);
-       //Only do this if we are building for 5535
-       msr.lo = 0x2;
-       msr.hi = 0x0;
-       wrmsr(VIP_GIO_MSR_SEL, msr);
 }
 
 static void dummy(void)

Modified: trunk/src/southbridge/amd/cs5536/early_setup.c
==============================================================================
--- trunk/src/southbridge/amd/cs5536/early_setup.c      Thu Dec 30 20:21:08 
2010        (r6224)
+++ trunk/src/southbridge/amd/cs5536/early_setup.c      Thu Dec 30 20:23:29 
2010        (r6225)
@@ -145,7 +145,7 @@
 {
        msr_t msr;
 
-       /* setup CPU interface serial to mode B to match CPU */
+       /* Setup CPU serial SouthBridge interface to mode C. */
        msr = rdmsr(GLPCI_SB_CTRL);
        msr.lo &= ~0x18;
        msr.lo |= 0x10;

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