-update gx2/northbridgeinit.c to lx standards
-remove not longer needed code from gx2/northbridge.c
Signed-off-by: Nils Jacobs <[email protected]>
Thanks, Nils.
Index: src/northbridge/amd/gx2/northbridge.c
===================================================================
--- src/northbridge/amd/gx2/northbridge.c (revision 6225)
+++ src/northbridge/amd/gx2/northbridge.c (working copy)
@@ -215,92 +215,6 @@
return sizem;
}
-/* these are the 8-bit attributes for controlling RCONF registers */
-#define CACHE_DISABLE (1<<0)
-#define WRITE_ALLOCATE (1<<1)
-#define WRITE_PROTECT (1<<2)
-#define WRITE_THROUGH (1<<3)
-#define WRITE_COMBINE (1<<4)
-#define WRITE_SERIALIZE (1<<5)
-
-/* ram has none of this stuff */
-#define RAM_PROPERTIES (0)
-#define DEVICE_PROPERTIES (WRITE_SERIALIZE|CACHE_DISABLE)
-#define ROM_PROPERTIES (WRITE_SERIALIZE|WRITE_PROTECT|CACHE_DISABLE)
-
-/* setup_gx2_cache
- *
- * Returns the amount of memory (in KB) available to the system. This is the
- * total amount of memory less the amount of memory reserved for SMM use.
- */
-static int setup_gx2_cache(void)
-{
- msr_t msr;
- unsigned long long val;
- int sizekbytes, sizereg;
-
- sizekbytes = sizeram() * 1024;
- printk(BIOS_DEBUG, "setup_gx2_cache: enable for %d KB\n", sizekbytes);
- /* build up the rconf word. */
- /* the SYSTOP bits 27:8 are actually the top bits from 31:12. Book fails to say that */
- /* set romrp */
- val = ((unsigned long long) ROM_PROPERTIES) << 56;
- /* make rom base useful for 1M roms */
- /* Flash base address -- sized for 1M for now */
- val |= ((unsigned long long) 0xfff00)<<36;
- /* set the devrp properties */
- val |= ((unsigned long long) DEVICE_PROPERTIES) << 28;
- /* Take our TOM, RIGHT shift 12, since it page-aligned, then LEFT-shift 8 for reg. */
- /* yank off memory for the SMM handler */
- sizekbytes -= SMM_SIZE;
- sizereg = sizekbytes;
- sizereg *= 1024; /* convert to bytes */
- sizereg >>= 12;
- sizereg <<= 8;
- val |= sizereg;
- val |= RAM_PROPERTIES;
- msr.lo = val;
- msr.hi = (val >> 32);
- printk(BIOS_DEBUG, "msr 0x%08X will be set to %08x:%08x\n", CPU_RCONF_DEFAULT, msr.hi, msr.lo);
- wrmsr(CPU_RCONF_DEFAULT, msr);
-
- enable_cache();
- wbinvd();
- return sizekbytes;
-}
-
-/* we have to do this here. We have not found a nicer way to do it */
-static void setup_gx2(void)
-{
- unsigned long tmp, tmp2;
- msr_t msr;
- unsigned long size_kb, membytes;
-
- size_kb = setup_gx2_cache();
-
- membytes = size_kb * 1024;
- /* NOTE! setup_gx2_cache returns the SIZE OF RAM - RAMADJUST!
- * so it is safe to use. You should NOT at this point call
- * sizeram() directly.
- */
-
- /* fixme: SMM MSR 0x10000026 and 0x400000023 */
- /* calculate the OFFSET field */
- tmp = membytes - SMM_OFFSET;
- tmp >>= 12;
- tmp <<= 8;
- tmp |= 0x20000000;
- tmp |= (SMM_OFFSET >> 24);
-
- /* calculate the PBASE and PMASK fields */
- tmp2 = (SMM_OFFSET << 8) & 0xFFF00000; /* shift right 12 then left 20 == left 8 */
- tmp2 |= (((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff);
- printk(BIOS_DEBUG, "MSR 0x%x is now 0x%lx:0x%lx\n", 0x10000026, tmp, tmp2);
- msr.hi = tmp;
- msr.lo = tmp2;
- wrmsr(0x10000026, msr);
-}
-
static void enable_shadow(device_t dev)
{
@@ -398,7 +312,6 @@
northbridge_init_early();
cpubug();
chipsetinit();
- setup_gx2();
print_conf();
do_vsmbios();
graphics_init();
Index: src/northbridge/amd/gx2/northbridgeinit.c
===================================================================
--- src/northbridge/amd/gx2/northbridgeinit.c (revision 6225)
+++ src/northbridge/amd/gx2/northbridgeinit.c (working copy)
@@ -1,3 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ * Copyright (C) 2010 Nils Jacobs
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
#include <console/console.h>
#include <arch/io.h>
#include <stdint.h>
@@ -25,7 +45,6 @@
{.desc_name=GLIU0_P2D_BM_1, .desc_type= BM,.hi= MSR_MC + 0x0,.lo=(0x80 << 20) + 0x0FFFE0}, /* 80000-9ffff to Mc */
{.desc_name=GLIU0_P2D_SC_0, .desc_type= SC_SHADOW,.hi= MSR_MC + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) A0000-Bffff handled by SoftVideo */
{.desc_name=GLIU0_P2D_R_0, .desc_type= R_SYSMEM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */
- {.desc_name=GLIU0_P2D_BMO_1, .desc_type= BMO_DMM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */
{.desc_name=GLIU0_P2D_BMO_0, .desc_type= BMO_SMM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */
{.desc_name=GLIU0_GLD_MSR_COH, .desc_type= OTHER,.hi= 0x0,.lo= GL0_CPU},
{.desc_name=GL_END, .desc_type= GL_END,.hi= 0x0,.lo= 0x0},
@@ -36,7 +55,6 @@
{.desc_name=GLIU1_P2D_BM_1, .desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= (0x80 << 20) + 0x0FFFE0},/* 80000-9ffff to Mc */
{.desc_name=GLIU1_P2D_SC_0, .desc_type= SC_SHADOW,.hi= MSR_GL0 + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) */
{.desc_name=GLIU1_P2D_R_0, .desc_type= R_SYSMEM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */
- {.desc_name=GLIU1_P2D_BM_4, .desc_type= BM_DMM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */
{.desc_name=GLIU1_P2D_BM_3, .desc_type= BM_SMM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */
{.desc_name=GLIU1_GLD_MSR_COH, .desc_type= OTHER,.hi= 0x0,.lo= GL1_GLIU0},
{.desc_name=GLIU1_IOD_SC_0, .desc_type= SCIO,.hi= (GL1_GLCP << 29) + 0x0,.lo= 0x033000F0}, /* FooGlue FPU 0xF0 */
@@ -100,9 +118,6 @@
{0xFFFFFFFF, {0xFFFFFFFF, 0xFFFFFFFF}}, /* END */
};
-/* do we have dmi or not? assume NO per AMD */
-int havedmi = 0;
-
static void writeglmsr(struct gliutable *gl)
{
msr_t msr;
@@ -110,10 +125,7 @@
msr.lo = gl->lo;
msr.hi = gl->hi;
wrmsr(gl->desc_name, msr); /* MSR - see table above */
- printk(BIOS_DEBUG, "%s: write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
- /* they do this, so we do this */
- msr = rdmsr(gl->desc_name);
- printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
+ printk(BIOS_DEBUG, "%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
}
static void ShadowInit(struct gliutable *gl)
@@ -141,73 +153,19 @@
sizebytes -= ((SMM_SIZE * 1024) + 1);
- if (havedmi)
- sizebytes -= DMM_SIZE * 1024 + 1;
-
/* 20 bit address The bottom 12 bits go into bits 20-31 in msr.lo
The top 8 bits go into 0-7 of msr.hi. */
- sizebytes -= 1;
+ sizebytes --;
msr.hi = (gl->hi & 0xFFFFFF00) | (sizebytes >> 24);
sizebytes <<= 8; /* move bits 23:12 in bits 31:20. */
sizebytes &= 0xFFF00000;
sizebytes |= 0x100; /* start at 1MB */
msr.lo = sizebytes;
wrmsr(gl->desc_name, msr); /* MSR - see table above */
- msr = rdmsr(gl->desc_name);
- printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__,
+ printk(BIOS_DEBUG, "%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__,
gl->desc_name, msr.hi, msr.lo);
}
-static void DMMGL0Init(struct gliutable *gl)
-{
- msr_t msr;
- int sizebytes = sizeram()<<20;
- long offset;
-
- if (! havedmi)
- return;
-
- printk(BIOS_DEBUG, "%s: %d bytes\n", __func__, sizebytes);
-
- sizebytes -= DMM_SIZE*1024;
- offset = sizebytes - DMM_OFFSET;
- printk(BIOS_DEBUG, "%s: offset is 0x%08lx\n", __func__, offset);
- offset >>= 12;
- msr.hi = (gl->hi) | (offset << 8);
- /* I don't think this is needed */
- msr.hi &= 0xffffff00;
- msr.hi |= (DMM_OFFSET >> 24);
- msr.lo = DMM_OFFSET << 8;
- msr.lo |= ((~(DMM_SIZE*1024)+1)>>12)&0xfffff;
-
- wrmsr(gl->desc_name, msr); /* MSR - See table above */
- msr = rdmsr(gl->desc_name);
- printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
-}
-
-static void DMMGL1Init(struct gliutable *gl)
-{
- msr_t msr;
-
- if (! havedmi)
- return;
-
- printk(BIOS_DEBUG, "%s:\n", __func__ );
-
- msr.hi = gl->hi;
- /* I don't think this is needed */
- msr.hi &= 0xffffff00;
- msr.hi |= (DMM_OFFSET >> 24);
- msr.lo = DMM_OFFSET << 8;
- /* hmm. AMD source has SMM here ... SMM, not DMM? We think DMM */
- printk(BIOS_ERR, "%s: warning, using DMM_SIZE even though AMD used SMM_SIZE\n", __func__);
- msr.lo |= ((~(DMM_SIZE*1024)+1)>>12)&0xfffff;
-
- wrmsr(gl->desc_name, msr); /* MSR - See table above */
- msr = rdmsr(gl->desc_name);
- printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
-}
-
static void SMMGL0Init(struct gliutable *gl)
{
msr_t msr;
@@ -216,24 +174,20 @@
sizebytes -= (SMM_SIZE * 1024);
- if (havedmi)
- sizebytes -= DMM_SIZE * 1024;
-
printk(BIOS_DEBUG, "%s: %d bytes\n", __func__, sizebytes);
offset = sizebytes - SMM_OFFSET;
- printk(BIOS_DEBUG, "%s: offset is 0x%08lx\n", __func__, offset);
- offset >>= 12;
+ offset = (offset >> 12) & 0x000FFFFF;
+ printk(BIOS_DEBUG, "%s: offset is 0x%08x\n", __func__, SMM_OFFSET);
- msr.hi = offset << 8;
+ msr.hi = offset << 8 | gl->hi;
msr.hi |= SMM_OFFSET >> 24;
msr.lo = SMM_OFFSET << 8;
msr.lo |= ((~(SMM_SIZE * 1024) + 1) >> 12) & 0xFFFFF;
wrmsr(gl->desc_name, msr); /* MSR - See table above */
- msr = rdmsr(gl->desc_name);
- printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
+ printk(BIOS_DEBUG, "%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
}
static void SMMGL1Init(struct gliutable *gl)
@@ -245,12 +199,11 @@
/* I don't think this is needed */
msr.hi &= 0xFFFFFF00;
msr.hi |= (SMM_OFFSET >> 24);
- msr.lo = SMM_OFFSET << 8;
+ msr.lo = (SMM_OFFSET << 8) & 0xFFF00000;
msr.lo |= ((~(SMM_SIZE * 1024) + 1) >> 12) & 0xFFFFF;
wrmsr(gl->desc_name, msr); /* MSR - See table above */
- msr = rdmsr(gl->desc_name);
- printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
+ printk(BIOS_DEBUG, "%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
}
static void GLIUInit(struct gliutable *gl)
@@ -258,7 +211,6 @@
while (gl->desc_type != GL_END) {
switch (gl->desc_type) {
default:
- /* For Unknown types: Write then read MSR */
writeglmsr(gl);
case SC_SHADOW: /* Check for a Shadow entry */
ShadowInit(gl);
@@ -268,14 +220,6 @@
SysmemInit(gl);
break;
- case BMO_DMM: /* check for a DMM entry */
- DMMGL0Init(gl);
- break;
-
- case BM_DMM: /* check for a DMM entry */
- DMMGL1Init(gl);
- break;
-
case BMO_SMM: /* check for a SMM entry */
SMMGL0Init(gl);
break;
@@ -330,7 +274,6 @@
* so we need a high page aligned addresss (pah) and low page aligned address (pal)
* pah is from msr.hi << 12 | msr.low >> 20. pal is msr.lo << 12
*/
- printk(BIOS_DEBUG, "GLPCI r1: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo, msr.hi);
pah = ((msr.hi & 0xFF) << 12) | ((msr.lo >> 20) & 0xFFF);
/* we have the page address. Now make it a page-aligned address */
pah <<= 12;
@@ -348,6 +291,7 @@
msr.hi = ((SMM_OFFSET + (SMM_SIZE * 1024 - 1)) >> 12) << GLPCI_RC_UPPER_TOP_SHIFT;
msr.lo = (SMM_OFFSET >> 12) << GLPCI_RC_LOWER_BASE_SHIFT;
msr.lo |= GLPCI_RC_LOWER_EN_SET | GLPCI_RC_LOWER_PF_SET;
+ printk(BIOS_DEBUG, "GLPCI R2: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo, msr.hi);
msrnum = GLPCI_RC2;
wrmsr(msrnum, msr);
@@ -391,7 +335,7 @@
/* we are ignoring the 5530 case for now, and perhaps forever. */
/* 553X NB Init */
-
+
/* Arbiter setup */
msrnum = GLPCI_ARB;
msr = rdmsr(msrnum);
@@ -448,33 +392,10 @@
struct msrinit *gating = ClockGatingDefault;
int i;
-#if 0
- mov cx, TOKEN_CLK_GATE
- NOSTACK bx, GetNVRAMValueBX
- cmp al, TVALUE_CG_OFF
- je gatingdone
-
- cmp al, TVALUE_CG_DEFAULT
- jb allon
- ja performance
- lea si, ClockGatingDefault
- jmp nextdevice
-
-allon:
- lea si, ClockGatingAllOn
- jmp nextdevice
-
-performance:
- lea si, ClockGatingPerformance
-#endif
-
for (i = 0; gating->msrnum != 0xFFFFFFFF; i++) {
msr = rdmsr(gating->msrnum);
- printk(BIOS_DEBUG, "%s: MSR 0x%08lx is 0x%08x:0x%08x\n", __func__, gating->msrnum, msr.hi, msr.lo);
msr.hi |= gating->msr.hi;
msr.lo |= gating->msr.lo;
- printk(BIOS_DEBUG, "%s: MSR 0x%08lx will be set to 0x%08x:0x%08x\n", __func__,
- gating->msrnum, msr.hi, msr.lo);
wrmsr(gating->msrnum, msr); /* MSR - See the table above */
gating += 1;
}
@@ -489,12 +410,9 @@
for (i = 0; prio->msrnum != 0xFFFFFFFF; i++) {
msr = rdmsr(prio->msrnum);
- printk(BIOS_DEBUG, "%s: MSR 0x%08lx is 0x%08x:0x%08x\n", __func__, prio->msrnum, msr.hi, msr.lo);
msr.hi |= prio->msr.hi;
msr.lo &= ~0xFFF;
msr.lo |= prio->msr.lo;
- printk(BIOS_DEBUG, "%s: MSR 0x%08lx will be set to 0x%08x:0x%08x\n", __func__,
- prio->msrnum, msr.hi, msr.lo);
wrmsr(prio->msrnum, msr); /* MSR - See the table above */
prio += 1;
}
@@ -507,7 +425,7 @@
*/
static uint64_t getShadow(void)
{
- msr_t msr;
+ msr_t msr = { 0, 0 };
msr = rdmsr(GLIU0_P2D_SC_0);
return ( ( (uint64_t) msr.hi ) << 32 ) | msr.lo;
@@ -614,7 +532,7 @@
}
}
-static void shadowRom(void)
+static void rom_shadow_settings(void)
{
uint64_t shadowSettings = getShadow();
shadowSettings &= (uint64_t) 0xFFFF00000000FFFFULL; /* Disable read & writes */
@@ -636,7 +554,7 @@
#define ROMBASE_RCONF_DEFAULT 0xFFFC0000
#define ROMRC_RCONF_DEFAULT 0x25
-static void RCONFInit(void)
+static void enable_L_cache(void)
{
struct gliutable *gl = 0;
int i;
@@ -680,6 +598,7 @@
/* now program RCONF_DEFAULT */
wrmsr(CPU_RCONF_DEFAULT, msr);
+ printk(BIOS_DEBUG, "CPU_RCONF_DEFAULT (1808): 0x%08X:0x%08X\n", msr.hi, msr.lo);
/* RCONF_BYPASS: Cache tablewalk properties and SMM header access properties. */
/* Set to match system memory cache properties. */
@@ -688,6 +607,24 @@
msr = rdmsr(CPU_RCONF_BYPASS);
msr.lo = (msr.lo & 0xFFFF0000) | (SysMemCacheProp << 8) | SysMemCacheProp;
wrmsr(CPU_RCONF_BYPASS, msr);
+ printk(BIOS_DEBUG, "CPU_RCONF_BYPASS (180A): 0x%08x : 0x%08x\n", msr.hi, msr.lo);
+}
+
+static void setup_gx2_cache(void)
+{
+ msr_t msr;
+
+ enable_L_cache();
+
+ /* Make sure all INVD instructions are treated as WBINVD. We do this
+ * because we've found some programs which require this behavior.
+ */
+ msr = rdmsr(CPU_DM_CONFIG0);
+ msr.lo |= DM_CONFIG0_LOWER_WBINVD_SET;
+ wrmsr(CPU_DM_CONFIG0, msr);
+
+ x86_enable_cache();
+ wbinvd();
}
uint32_t get_systop(void)
@@ -717,35 +654,27 @@
/* Core Logic initialization: Host bridge. */
void northbridge_init_early(void)
{
- msr_t msr;
int i;
printk(BIOS_DEBUG, "Enter %s\n", __func__);
for (i = 0; gliutables[i]; i++)
GLIUInit(gliutables[i]);
- GeodeLinkPriority();
-
- shadowRom();
-
- RCONFInit();
-
- /* The cacheInit function in GeodeROM tests cache and, among other things,
- * makes sure all INVD instructions are treated as WBINVD. We do this
- * because we've found some programs which require this behavior.
- * That subset of cacheInit() is implemented here:
- */
- msr = rdmsr(CPU_DM_CONFIG0);
- msr.lo |= DM_CONFIG0_LOWER_WBINVD_SET;
- wrmsr(CPU_DM_CONFIG0, msr);
-
/* Now that the descriptor to memory is set up. */
/* The memory controller needs one read to synch its lines before it can be used. */
i = *(int *) 0;
+ GeodeLinkPriority();
+
+ setup_gx2_cache();
+
+ rom_shadow_settings();
+
GLPCIInit();
+
ClockGatingInit();
- __asm__("FINIT\n");
+
+ __asm__ __volatile__("FINIT\n");
printk(BIOS_DEBUG, "Exit %s\n", __func__);
}
--
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