Author: zbao Date: Tue Jan 25 07:06:58 2011 New Revision: 6297 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6297
Log: Set the SB800 SATA PHY correctly. Signed-off-by: Zheng Bao <[email protected]> Acked-by: Zheng Bao <[email protected]> Modified: trunk/src/southbridge/amd/sb800/sata.c Modified: trunk/src/southbridge/amd/sb800/sata.c ============================================================================== --- trunk/src/southbridge/amd/sb800/sata.c Mon Jan 24 22:27:22 2011 (r6296) +++ trunk/src/southbridge/amd/sb800/sata.c Tue Jan 25 07:06:58 2011 (r6297) @@ -53,6 +53,15 @@ return 0; } +static const u32 sata_phy[][3] = { + {0x0056A607, 0x00061400, 0x00061302}, /* port 0 */ + {0x0056A607, 0x00061400, 0x00061302}, /* port 1 */ + {0x0056A607, 0x00061402, 0x00064300}, /* port 2 */ + {0x0056A607, 0x00061402, 0x00064300}, /* port 3 */ + {0x0056A700, 0x00061502, 0x00064302}, /* port 4 */ + {0x0056A700, 0x00061502, 0x00064302} /* port 5 */ +}; + static void sata_init(struct device *dev) { u8 byte; @@ -139,14 +148,14 @@ pci_write_config8(dev, 0x46, 0x20); /* RPR8.4 */ - /* Port 0 */ + /* Port 0 - 5 */ for (i = 0; i < 6; i++) { pci_write_config16(dev, 0x84, 0x3006 | i << 9); - pci_write_config32(dev, 0x94, 0x0056A700); + pci_write_config32(dev, 0x94, sata_phy[i][0]); /* Gen 3 */ pci_write_config16(dev, 0x84, 0x2006 | i << 9); - pci_write_config32(dev, 0x94, 0x00061400); + pci_write_config32(dev, 0x94, sata_phy[i][1]); /* Gen 2 */ pci_write_config16(dev, 0x84, 0x1006 | i << 9); - pci_write_config32(dev, 0x94, 0x00061302); + pci_write_config32(dev, 0x94, sata_phy[i][2]); /* Gen 1 */ } /* Enable the I/O, MM, BusMaster access for SATA */ -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
