Hi all,
Attached patch adds support for CMOS options which can alter DDR Memory, HT GPU,
and Sideport Voltages. Also as a quick hack it can change CPU base frequency
from 200MHz to something else.
I think this would be nice to show on FOSDEM.It could be extended so not only
CPU PLL is programmed but also PCIe etc, also one could adjust the DDR divisors
so the memory runs still like on 200MHz (same for HT). Also FID could be
changed, but this is not implemented yet. The CPU voltage changes are possible
too. It is just a question of writing to SIO...
boot_option = Fallback
last_boot = Fallback
ECC_memory = Disable
baud_rate = 115200
debug_level = Info
power_on_after_fail = Disable
hw_scrubber = Disable
nmi = Disable
iommu = Enable
interleave_chip_selects = Enable
multi_core = Enable
slow_cpu = off
max_mem_clock = DDR400
cmos_defaults_loaded = Disable
ht_voltage = 1.30V
sideport_voltage = 1.82V
gpu_voltage = 1.10V
memory_voltage = 2.60V
cpu_freq = 210MHz
Although it is bit hackish I do
Signed-off-by: Rudolf Marek <[email protected]>
If someone has similar/same board and has more time to work on this it would be
very nice!
Not sure If I will be able to prepare it to comittable state before FOSDEM.
Thanks,
Rudolf
Index: src/southbridge/amd/sb700/smbus.h
===================================================================
--- src/southbridge/amd/sb700/smbus.h (revision 6298)
+++ src/southbridge/amd/sb700/smbus.h (working copy)
@@ -60,6 +60,7 @@
int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val);
int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val);
+int do_smbus_write_word(u32 smbus_io_base, u32 device, u32 address, u16 val);
#endif
Index: src/southbridge/amd/sb700/smbus.c
===================================================================
--- src/southbridge/amd/sb700/smbus.c (revision 6298)
+++ src/southbridge/amd/sb700/smbus.c (working copy)
@@ -177,6 +177,38 @@
return 0;
}
+int do_smbus_write_word(u32 smbus_io_base, u32 device, u32 address, u16 val)
+{
+ u8 byte;
+
+ if (smbus_wait_until_ready(smbus_io_base) < 0) {
+ return -2; /* not ready */
+ }
+
+ /* set the command/address... */
+ outb(address & 0xff, smbus_io_base + SMBHSTCMD);
+
+ /* set the device I'm talking too */
+ outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR);
+
+ /* output value */
+ outb(val & 0xff, smbus_io_base + SMBHSTDAT0);
+ outb(val >> 8, smbus_io_base + SMBHSTDAT1);
+
+ byte = inb(smbus_io_base + SMBHSTCTRL);
+ byte &= 0xe3; /* Clear [4:2] */
+ byte |= (1 << 3) | (1 << 2) | (1 << 6); /* Word data read/write command, start the command */
+ outb(byte, smbus_io_base + SMBHSTCTRL);
+
+ /* poll for transaction completion */
+ if (smbus_wait_until_done(smbus_io_base) < 0) {
+ return -3; /* timeout or error */
+ }
+
+ return 0;
+}
+
+
static void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val)
{
u32 tmp;
Index: src/southbridge/amd/sb700/early_setup.c
===================================================================
--- src/southbridge/amd/sb700/early_setup.c (revision 6298)
+++ src/southbridge/amd/sb700/early_setup.c (working copy)
@@ -619,6 +619,11 @@
sb700_acpi_init();
}
+static int smbus_write_word(u32 device, u32 address, u16 val) {
+ return do_smbus_write_word(SMBUS_IO_BASE, device, address, val);
+}
+
+
static int smbus_read_byte(u32 device, u32 address)
{
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
Index: src/superio/winbond/w83627dhg/superio.c
===================================================================
--- src/superio/winbond/w83627dhg/superio.c (revision 6298)
+++ src/superio/winbond/w83627dhg/superio.c (working copy)
@@ -81,7 +81,7 @@
pnp_enter_ext_func_mode(dev);
pnp_set_logical_device(dev);
- pnp_set_enable(dev, 0);
+ pnp_set_enable(dev, 1);
pnp_exit_ext_func_mode(dev);
}
Index: src/mainboard/asrock/939a785gmh/romstage.c
===================================================================
--- src/mainboard/asrock/939a785gmh/romstage.c (revision 6298)
+++ src/mainboard/asrock/939a785gmh/romstage.c (working copy)
@@ -48,6 +48,9 @@
#include "southbridge/amd/sb700/early_setup.c"
#include "northbridge/amd/amdk8/debug.c" /* After sb700/early_setup.c! */
+#include "option_table.h"
+
+
#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
#define GPIO2345_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V)
@@ -74,7 +77,20 @@
static void sio_init(void)
{
u8 reg;
+ u8 mem_volt = read_option(CMOS_VSTART_memory_voltage, CMOS_VLEN_memory_voltage, 0);
+ u8 ht_volt = read_option(CMOS_VSTART_ht_voltage, CMOS_VLEN_ht_voltage, 0);
+ u8 gpu_volt = read_option(CMOS_VSTART_gpu_voltage, CMOS_VLEN_gpu_voltage, 0);
+ u8 sideport_volt = read_option(CMOS_VSTART_sideport_voltage, CMOS_VLEN_sideport_voltage, 0);
+ printk(BIOS_DEBUG, "Memory on 2.%02dV GPU on 1.%02dV Sideport on 1.%02dV HT on 1.%02dV\n",
+ (mem_volt * 5) + 60, (gpu_volt * 5) + 10, (sideport_volt) ? 92 : 82, (ht_volt) ? 35 : 30);
+
+ /* remap to match the bit meanings */
+ mem_volt = 7 - mem_volt;
+ ht_volt = !ht_volt;
+ sideport_volt = !sideport_volt;
+ gpu_volt = 7 - gpu_volt;
+
pnp_enter_ext_func_mode(GPIO2345_DEV);
pnp_set_logical_device(GPIO2345_DEV);
@@ -98,7 +114,7 @@
*/
pnp_write_config(GPIO2345_DEV, 0x30, 0x07); /* Enable GPIO 2,3,4. */
pnp_write_config(GPIO2345_DEV, 0xe3, 0xf6); /* dir of GPIO2 11110110*/
- pnp_write_config(GPIO2345_DEV, 0xe4, 0x0e); /* data */
+ pnp_write_config(GPIO2345_DEV, 0xe4, ((gpu_volt & 1) << 3) | sideport_volt); /* data */
pnp_write_config(GPIO2345_DEV, 0xe5, 0x00); /* No inversion */
/* GPIO30 - unknown output, set to 0
@@ -110,8 +126,8 @@
GPIO36 - input = HT voltage 1.30V output (low) = HT voltage 1.35V
GP37 - unknown input NC? */
- pnp_write_config(GPIO2345_DEV, 0xf0, 0xd6); /* dir of GPIO3 11010110*/
- pnp_write_config(GPIO2345_DEV, 0xf1, 0x96); /* data */
+ pnp_write_config(GPIO2345_DEV, 0xf0, 0x96 | (ht_volt << 6)); /* dir of GPIO3 10010110*/
+ pnp_write_config(GPIO2345_DEV, 0xf1, 0x0); /* data */
pnp_write_config(GPIO2345_DEV, 0xf2, 0x00); /* No inversion */
/* GPO40 - mgpuV bit2
@@ -119,12 +135,12 @@
GPO42 - IRTX
GPO43 - IRRX
GPIO44 - memory voltage bit2 (input/outputlow)
- GPIO45 - memory voltage bit1 (2.60 (000) - 2.95 (111))
+ GPIO45 - memory voltage bit1 (2.60 (111) - 2.95 (000))
GPIO46 - memory voltage bit0
GPIO47 - unknown input? */
- pnp_write_config(GPIO2345_DEV, 0xf4, 0xd0); /* dir of GPIO4 11010000 */
- pnp_write_config(GPIO2345_DEV, 0xf5, 0x83); /* data */
+ pnp_write_config(GPIO2345_DEV, 0xf4, (1 << 7) | ((mem_volt & 1) << 6) | ((mem_volt & 2) << 4) | ((mem_volt & 4) << 2)); /* dir of GPIO4 11010000 */
+ pnp_write_config(GPIO2345_DEV, 0xf5, (gpu_volt & 2) | ((gpu_volt & 4) >> 2)); /* data */
pnp_write_config(GPIO2345_DEV, 0xf6, 0x00); /* No inversion */
pnp_write_config(GPIO2345_DEV, 0xf7, 0x00); /* MFC */
@@ -156,7 +172,6 @@
enable_rs780_dev8();
sb700_lpc_init();
- sio_init();
w83627dhg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
@@ -166,6 +181,7 @@
#endif
console_init();
+ sio_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
@@ -188,6 +204,14 @@
rs780_early_setup();
sb700_early_setup();
+ {
+ int a = 0;
+ u8 cpu_freq = read_option(CMOS_VSTART_cpu_freq, CMOS_VLEN_cpu_freq, 0);
+ a = smbus_write_word(0x69, 0x3, 0xe001 | (cpu_freq << 8));
+ printk(BIOS_INFO, "CPU Freq is %dMHz\n",(cpu_freq*5)+200);
+ }
+
+
/* Check to see if processor is capable of changing FIDVID */
/* otherwise it will throw a GP# when reading FIDVID_STATUS */
cpuid1 = cpuid(0x80000007);
Index: src/mainboard/asrock/939a785gmh/cmos.layout
===================================================================
--- src/mainboard/asrock/939a785gmh/cmos.layout (revision 6298)
+++ src/mainboard/asrock/939a785gmh/cmos.layout (working copy)
@@ -45,32 +45,40 @@
#95 1 r 0 disable_clock_updates
#96 288 r 0 temporary_filler
0 384 r 0 reserved_memory
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
384 1 e 4 boot_option
385 1 e 4 last_boot
386 1 e 1 ECC_memory
388 4 r 0 reboot_bits
+
+# -----------------------------------------------------------------
+# coreboot config options: console
392 3 e 5 baud_rate
-395 1 e 1 hw_scrubber
-396 1 e 1 interleave_chip_selects
-397 2 e 8 max_mem_clock
-399 1 e 2 multi_core
-400 1 e 1 power_on_after_fail
-412 4 e 6 debug_level
-416 4 e 7 boot_first
-420 4 e 7 boot_second
-424 4 e 7 boot_third
-428 4 h 0 boot_index
-432 8 h 0 boot_countdown
-440 4 e 9 slow_cpu
-444 1 e 1 nmi
-445 1 e 1 iommu
-728 256 h 0 user_data
+395 4 e 6 debug_level
+
+# 400 is century byte
+400 8 r 0 century_byte
+408 1 e 1 power_on_after_fail
+410 1 e 1 hw_scrubber
+412 1 e 1 nmi
+413 1 e 1 iommu
+414 1 e 1 interleave_chip_selects
+415 1 e 2 multi_core
+416 4 e 9 slow_cpu
+420 2 e 8 max_mem_clock
+422 1 e 1 cmos_defaults_loaded
+423 1 e 13 ht_voltage
+424 1 e 12 sideport_voltage
+425 3 e 10 gpu_voltage
+428 3 e 11 memory_voltage
+432 4 e 14 cpu_freq
+
+# coreboot config options: check sums
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 amd_reserved
-
-
enumerations
#ID value text
@@ -88,17 +96,17 @@
5 5 4800
5 6 2400
5 7 1200
+6 1 Emergency
+6 2 Alert
+6 3 Critical
+6 4 Error
+6 5 Warning
6 6 Notice
6 7 Info
6 8 Debug
6 9 Spew
-7 0 Network
-7 1 HDD
-7 2 Floppy
-7 8 Fallback_Network
-7 9 Fallback_HDD
-7 10 Fallback_Floppy
-#7 3 ROM
+7 0 No
+7 1 Yes
8 0 DDR400
8 1 DDR333
8 2 DDR266
@@ -112,8 +120,66 @@
9 6 25.0%
9 7 12.5%
+#GPU voltage (0 and 7 are swapped)
+10 0 1.10V
+10 1 1.15V
+10 2 1.20V
+10 3 1.25V
+10 4 1.30V
+10 5 1.35V
+10 6 1.40V
+10 7 1.45V
+
+
+#10 7 1.45V
+#10 1 1.40V
+#10 4 1.35V
+#10 5 1.30V
+#10 2 1.25V
+#10 3 1.20V
+#10 6 1.15V
+#10 0 1.10V
+
+#ddr voltage 1 = input , 0= output + low (0, 7 swapped)
+
+11 0 2.60V
+11 1 2.65V
+11 2 2.70V
+11 3 2.75V
+11 4 2.80V
+11 5 2.85V
+11 6 2.90V
+11 7 2.95V
+
+#11 7 2.95V
+#11 4 2.90V
+#11 2 2.85V
+#11 6 2.80V
+#11 1 2.75V
+#11 5 2.70V
+#11 3 2.65V
+#11 0 2.60V
+
+#sideport voltage (swapped mapping)
+12 0 1.82V
+12 1 1.92V
+
+#HT voltage (swapped mapping)
+13 0 1.30V
+13 1 1.35V
+
+#CPU overclock
+14 0 200MHz
+14 1 205MHz
+14 2 210MHz
+14 3 215MHz
+14 4 220MHz
+
+
+
+# -----------------------------------------------------------------
checksums
+#start, end, location
checksum 392 983 984
-
--
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