See patch for details. I have an ASUS K8V-X SE with the named NB, and this patch is sufficient to get the HT link working properly, and to get a working V-Link with the southbridge. The modifications in the vt8237r directory allow the respective SB to find the K8T800 and K8M800 NBs.
I will need someone with a K8T890 to test this patch to make sure it doesn't break anything on the K8T890 side. Alex
Extended K8T890 driver to include the K8T800 and K8M800 northbridges. According to the datasheet, the K8T890 and K8T800 are similar enough to be able to use the same initialization code. At least for the K8T800, this is sufficient to have a working HT link with the CPU, and to initialise the V-Link to the southbridge. Signed-off-by Alexandru Gagniuc <[email protected]> --- Index: src/southbridge/via/vt8237r/vt8237r.c =================================================================== --- src/southbridge/via/vt8237r/vt8237r.c (revision 6323) +++ src/southbridge/via/vt8237r/vt8237r.c (working copy) @@ -40,9 +40,9 @@ if (regval != what) { print_debug("Writeback to "); print_debug_hex8(where); - print_debug("failed "); + print_debug(" failed "); print_debug_hex8(regval); - print_debug("\n "); /* TODO: Drop the space? */ + print_debug("\n"); } } #else Index: src/southbridge/via/vt8237r/ctrl.c =================================================================== --- src/southbridge/via/vt8237r/ctrl.c (revision 6323) +++ src/southbridge/via/vt8237r/ctrl.c (working copy) @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2008 Rudolf Marek <[email protected]> + * Copyright (C) 2011 Alexandru Gagniuc <[email protected]> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -32,9 +33,15 @@ device_t devfun3; devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8T890CE_3, 0); + PCI_DEVICE_ID_VIA_K8T800_DRAM, 0); if (!devfun3) devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_K8M800_DRAM, 0); + if (!devfun3) + devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_K8T890CE_3, 0); + if (!devfun3) + devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8M890CE_3, 0); if (!devfun3) devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, @@ -108,16 +115,25 @@ device_t devfun7; devfun7 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8T890CE_7, 0); + PCI_DEVICE_ID_VIA_K8T800_NB_SB_CTR, 0); if (!devfun7) devfun7 = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_K8M800_NB_SB_CTR, 0); + if (!devfun7) + devfun7 = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_K8T890CE_7, 0); + if (!devfun7) + devfun7 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8M890CE_7, 0); if (!devfun7) devfun7 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8T890CF_7, 0); /* No pairing NB was found. */ if (!devfun7) + { + print_debug("vt8237s_vlink_init: No pairing NB was found.\n"); return; + } /* * This init code is valid only for the VT8237S! For different @@ -174,16 +190,25 @@ device_t devfun7; devfun7 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8T890CE_7, 0); + PCI_DEVICE_ID_VIA_K8T800_NB_SB_CTR, 0); if (!devfun7) devfun7 = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_K8M800_NB_SB_CTR, 0); + if (!devfun7) + devfun7 = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_K8T890CE_7, 0); + if (!devfun7) + devfun7 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8M890CE_7, 0); if (!devfun7) devfun7 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8T890CF_7, 0); /* No pairing NB was found. */ if (!devfun7) + { + print_debug("vt8237a_vlink_init: No pairing NB was found.\n"); return; + } /* * This init code is valid only for the VT8237A! For different Index: src/southbridge/via/Makefile.inc =================================================================== --- src/southbridge/via/Makefile.inc (revision 6323) +++ src/southbridge/via/Makefile.inc (working copy) @@ -1,3 +1,5 @@ +subdirs-$(CONFIG_SOUTHBRIDGE_VIA_K8T800) += k8t890 +subdirs-$(CONFIG_SOUTHBRIDGE_VIA_K8M800) += k8t890 subdirs-$(CONFIG_SOUTHBRIDGE_VIA_K8T890) += k8t890 subdirs-$(CONFIG_SOUTHBRIDGE_VIA_K8M890) += k8t890 subdirs-$(CONFIG_SOUTHBRIDGE_VIA_VT8231) += vt8231 Index: src/southbridge/via/k8t890/romstrap.inc =================================================================== --- src/southbridge/via/k8t890/romstrap.inc (revision 6323) +++ src/southbridge/via/k8t890/romstrap.inc (working copy) @@ -33,7 +33,28 @@ * Below are some Dev0 Func2 HT control registers values, * depending on strap pin, one of below lines is used. */ +#if CONFIG_SOUTHBRIDGE_VIA_K8M800 || CONFIG_SOUTHBRIDGE_VIA_K8T800 + tblpointer: +.long 0x50220000, 0X619707C2 +.long 0x50220000, 0X619707C2 +.long 0x50220000, 0X619707C2 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 +.long 0x0 + +#elif CONFIG_SOUTHBRIDGE_VIA_K8M890 || CONFIG_SOUTHBRIDGE_VIA_K8T890 + +tblpointer: .long 0x504400AA, 0x61970FC2 //;200M .long 0x504400AA, 0x61970FC2 //;400M .long 0x504400AA, 0x61970FC2 //;600M @@ -50,6 +71,7 @@ .long 0x0 .long 0x0 +#endif /* * The pointer to above table should be at 0xffffd, * the table itself MUST be aligned to 128B it seems! Index: src/southbridge/via/k8t890/Kconfig =================================================================== --- src/southbridge/via/k8t890/Kconfig (revision 6323) +++ src/southbridge/via/k8t890/Kconfig (working copy) @@ -1,3 +1,9 @@ +config SOUTHBRIDGE_VIA_K8M800 #K8M800 not tested + bool + +config SOUTHBRIDGE_VIA_K8T800 + bool + config SOUTHBRIDGE_VIA_K8M890 bool @@ -40,5 +46,5 @@ config ID_SECTION_OFFSET hex - default 0x80 if SOUTHBRIDGE_VIA_K8M890 || SOUTHBRIDGE_VIA_K8T890 + default 0x80 if SOUTHBRIDGE_VIA_K8M890 || SOUTHBRIDGE_VIA_K8T890 || SOUTHBRIDGE_VIA_K8M800 || SOUTHBRIDGE_VIA_K8T800 Index: src/southbridge/via/k8t890/early_car.c =================================================================== --- src/southbridge/via/k8t890/early_car.c (revision 6323) +++ src/southbridge/via/k8t890/early_car.c (working copy) @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007 Rudolf Marek <[email protected]> + * Copyright (C) 2011 Alexandru Gagniuc <[email protected]> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -25,7 +26,7 @@ #include <stdlib.h> #include <cbmem.h> #include <arch/io.h> -#include "k8t890.h" +#include "k8x8xx.h" /* The 256 bytes of NVRAM for S3 storage, 256B aligned */ #define K8T890_NVRAM_IO_BASE 0xf00 @@ -66,7 +67,15 @@ ldtnr = 2; } +#if defined(CONFIG_SOUTHBRIDGE_VIA_K8M800) + print_debug("K8M800 found at LDT "); +#elif defined(CONFIG_SOUTHBRIDGE_VIA_K8T800) + print_debug("K8T800 found at LDT "); +#elif defined(CONFIG_SOUTHBRIDGE_VIA_K8M890) + print_debug("K8M890 found at LDT "); +#elif defined(CONFIG_SOUTHBRIDGE_VIA_K8T890) print_debug("K8T890 found at LDT "); +#endif print_debug_hex8(ldtnr); /* get the maximum widths for both sides */ Index: src/southbridge/via/k8t890/host_ctrl.c =================================================================== --- src/southbridge/via/k8t890/host_ctrl.c (revision 6323) +++ src/southbridge/via/k8t890/host_ctrl.c (working copy) @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007 Rudolf Marek <[email protected]> + * Copyright (C) 2011 Alexandru Gagniuc <[email protected]> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -24,15 +25,13 @@ #include <console/console.h> #include <cbmem.h> #include <arch/io.h> -#include "k8t890.h" +#include "k8x8xx.h" /* this may be later merged */ /* This fine tunes the HT link settings, which were loaded by ROM strap. */ -static void host_ctrl_enable_k8t890(struct device *dev) +static void host_ctrl_enable_k8t8xx(struct device *dev) { - dump_south(dev); - /* * Bit 4 is reserved but set by AW. Set PCI to HT outstanding * requests to 3. @@ -85,11 +84,12 @@ writeback(dev, 0xc4, 0x50); writeback(dev, 0xc5, 0x50); dump_south(dev); } /* This fine tunes the HT link settings, which were loaded by ROM strap. */ -static void host_ctrl_enable_k8m890(struct device *dev) { +static void host_ctrl_enable_k8m8xx(struct device *dev) { /* * Set PCI to HT outstanding requests to 03. @@ -126,7 +126,7 @@ .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .enable = host_ctrl_enable_k8t890, + .enable = host_ctrl_enable_k8t8xx, .ops_pci = 0, }; @@ -134,17 +134,29 @@ .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .enable = host_ctrl_enable_k8m890, + .enable = host_ctrl_enable_k8m8xx, .ops_pci = 0, }; -static const struct pci_driver northbridge_driver_t __pci_driver = { +static const struct pci_driver northbridge_driver_t800 __pci_driver = { .ops = &host_ctrl_ops_t, .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T800_HOST_CTR, +}; + +static const struct pci_driver northbridge_driver_m800 __pci_driver = { + .ops = &host_ctrl_ops_m, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8M800_HOST_CTR, +}; + +static const struct pci_driver northbridge_driver_t890 __pci_driver = { + .ops = &host_ctrl_ops_t, + .vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_K8T890CE_2, }; -static const struct pci_driver northbridge_driver_m __pci_driver = { +static const struct pci_driver northbridge_driver_m890 __pci_driver = { .ops = &host_ctrl_ops_m, .vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_K8M890CE_2, Index: src/southbridge/via/k8t890/ctrl.c =================================================================== --- src/southbridge/via/k8t890/ctrl.c (revision 6323) +++ src/southbridge/via/k8t890/ctrl.c (working copy) @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007 Rudolf Marek <[email protected]> + * Copyright (C) 2011 Alexandru Gagniuc <[email protected]> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -22,6 +23,7 @@ #include <device/pci_ops.h> #include <device/pci_ids.h> #include <console/console.h> +#include "k8x8xx.h" /* We support here K8M890/K8T890 and VT8237R PCI1/Vlink which setup is not in separate * PCI device 0:11.7, but it is mapped to PCI 0:0.7 (0x70-0x7c for PCI1) @@ -32,20 +34,31 @@ u8 regm, regm3; device_t devfun3; - + devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8T890CE_3, 0); + PCI_DEVICE_ID_VIA_K8T800_DRAM, 0); if (!devfun3) devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_K8M800_DRAM, 0); + + if (!devfun3) + devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_K8T890CE_3, 0); + + if (!devfun3) + devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8T890CF_3, 0); if (!devfun3) devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8M890CE_3, 0); + + if(!devfun3) + die("\n vt8237r_cfg: Unable to find K8x8xx bridge via PCI scan. Stopping.\n"); pci_write_config8(dev, 0x70, 0xc2); - + /* PCI Control */ pci_write_config8(dev, 0x72, 0xee); pci_write_config8(dev, 0x73, 0x01); @@ -87,6 +100,7 @@ /* Shadow page F + memhole copy */ regm = pci_read_config8(devfun3, 0x83); pci_write_config8(dev, 0x63, regm3 | (regm & 0x3F)); + } @@ -143,8 +157,10 @@ pci_write_config8(dev, 0x48, 0xa3); } -static void ctrl_init(struct device *dev) { +static void ctrl_init(struct device *dev) +{ + print_debug("K8x8xx: Initializing V-Link to VT8237R sb: "); /* TODO: Fix some ordering issue fo V-link set Rx77[6] and PCI1_Rx4F[0] should to 1 */ @@ -161,7 +177,13 @@ if (devsb) { vt8237r_vlink_init(dev); vt8237r_cfg(dev, devsb); + } else { + print_debug("VT8237R LPC not found !\n"); + return; } + print_debug(" Done\n"); } @@ -173,19 +195,31 @@ .ops_pci = 0, }; -static const struct pci_driver northbridge_driver_t __pci_driver = { +static const struct pci_driver northbridge_driver_t800 __pci_driver = { .ops = &ctrl_ops, .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T800_NB_SB_CTR, +}; + +static const struct pci_driver northbridge_driver_m800 __pci_driver = { + .ops = &ctrl_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8M800_NB_SB_CTR, +}; + +static const struct pci_driver northbridge_driver_t890 __pci_driver = { + .ops = &ctrl_ops, + .vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_K8T890CE_7, }; -static const struct pci_driver northbridge_driver_tcf __pci_driver = { +static const struct pci_driver northbridge_driver_t890cf __pci_driver = { .ops = &ctrl_ops, .vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_K8T890CF_7, }; -static const struct pci_driver northbridge_driver_m __pci_driver = { +static const struct pci_driver northbridge_driver_m890 __pci_driver = { .ops = &ctrl_ops, .vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_K8M890CE_7, Index: src/southbridge/via/k8t890/k8t890.h =================================================================== --- src/southbridge/via/k8t890/k8t890.h (revision 6323) +++ src/southbridge/via/k8t890/k8t890.h (working copy) @@ -41,6 +41,7 @@ #ifdef __PRE_RAM__ u8 k8t890_early_setup_ht(void); +#define k8x8xx_early_setup_ht() k8t890_early_setup_ht() #else #include <device/device.h> #if 0 Index: src/southbridge/via/k8t890/chrome.c =================================================================== --- src/southbridge/via/k8t890/chrome.c (revision 6323) +++ src/southbridge/via/k8t890/chrome.c (working copy) @@ -23,7 +23,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <string.h> /* for memset */ -#include "k8t890.h" +#include "k8x8xx.h" #if CONFIG_VGA #include <pc80/vga_io.h> @@ -169,6 +169,6 @@ static const struct pci_driver unichrome_driver __pci_driver = { .ops = &chrome_ops, - .vendor = 0x1106, + .vendor = PCI_VENDOR_ID_VIA, .device = 0x3230, }; Index: src/southbridge/via/k8t890/host.c =================================================================== --- src/southbridge/via/k8t890/host.c (revision 6323) +++ src/southbridge/via/k8t890/host.c (working copy) @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007 Rudolf Marek <[email protected]> + * Copyright (C) 2011 Alexandru Gagniuc <[email protected]> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -22,13 +23,15 @@ #include <device/pci_ops.h> #include <device/pci_ids.h> #include <console/console.h> -#include "k8t890.h" +#include "k8x8xx.h" static void host_enable(struct device *dev) { /* Multiple function control */ pci_write_config8(dev, K8T890_MULTIPLE_FN_EN, 0x01); + print_debug(" VIA_X_0 device dump:\n"); + dump_south(dev); } @@ -70,19 +73,31 @@ .ops_pci = 0, }; -static const struct pci_driver northbridge_driver_t __pci_driver = { +static const struct pci_driver northbridge_driver_t800 __pci_driver = { .ops = &host_ops_t, .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T800_HT_AGP_CTR, +}; + +static const struct pci_driver northbridge_driver_m800 __pci_driver = { + .ops = &host_ops_m, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8M800_HT_AGP_CTR, +}; + +static const struct pci_driver northbridge_driver_t890 __pci_driver = { + .ops = &host_ops_t, + .vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_K8T890CE_0, }; -static const struct pci_driver northbridge_driver_tcf __pci_driver = { +static const struct pci_driver northbridge_driver_t890cf __pci_driver = { .ops = &host_ops_t, .vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_K8T890CF_0, }; -static const struct pci_driver northbridge_driver_m __pci_driver = { +static const struct pci_driver northbridge_driver_m890 __pci_driver = { .ops = &host_ops_m, .vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_K8M890CE_0, Index: src/southbridge/via/k8t890/traf_ctrl.c =================================================================== --- src/southbridge/via/k8t890/traf_ctrl.c (revision 6323) +++ src/southbridge/via/k8t890/traf_ctrl.c (working copy) @@ -138,6 +138,9 @@ .ops_pci = 0, }; +/* K8X800 chipsets have no APIC; no 800 PCI ids here */ + + static const struct pci_driver northbridge_driver_t __pci_driver = { .ops = &traf_ctrl_ops_t, .vendor = PCI_VENDOR_ID_VIA, Index: src/southbridge/via/k8t890/dram.c =================================================================== --- src/southbridge/via/k8t890/dram.c (revision 6323) +++ src/southbridge/via/k8t890/dram.c (working copy) @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007 Rudolf Marek <[email protected]> + * Copyright (C) 2011 Alexandru Gagniuc <[email protected]> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -25,7 +26,7 @@ #include <cpu/amd/mtrr.h> #include <pc80/mc146818rtc.h> #include <bitops.h> -#include "k8t890.h" +#include "k8x8xx.h" static void dram_enable(struct device *dev) { @@ -34,9 +35,9 @@ /* * Enable Lowest Interrupt arbitration for APIC, enable NB APIC - * decoding, MSI support, no SMRAM, compatible SMM. + * decoding, MSI support, no SMRAM, compatible SMM. */ @@ -64,6 +65,9 @@ /* The Address Next to the Last Valid DRAM Address */ pci_write_config16(dev, 0x88, (msr.lo >> 24) | reg); } @@ -110,6 +114,8 @@ k8m890_host_fb_size_get(void) { struct device *dev = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_K8M800_DRAM, 0); + if(!dev) dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8M890CE_3, 0); unsigned char tmp; @@ -164,19 +170,31 @@ .ops_pci = 0, }; -static const struct pci_driver northbridge_driver_t __pci_driver = { +static const struct pci_driver northbridge_driver_t800 __pci_driver = { .ops = &dram_ops_t, .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T800_DRAM, +}; + +static const struct pci_driver northbridge_driver_m800 __pci_driver = { + .ops = &dram_ops_m, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8M800_DRAM, +}; + +static const struct pci_driver northbridge_driver_t890 __pci_driver = { + .ops = &dram_ops_t, + .vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_K8T890CE_3, }; -static const struct pci_driver northbridge_driver_tcf __pci_driver = { +static const struct pci_driver northbridge_driver_t890cf __pci_driver = { .ops = &dram_ops_t, .vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_K8T890CF_3, }; -static const struct pci_driver northbridge_driver_m __pci_driver = { +static const struct pci_driver northbridge_driver_m890 __pci_driver = { .ops = &dram_ops_m, .vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_K8M890CE_3, Index: src/southbridge/via/k8t890/error.c =================================================================== --- src/southbridge/via/k8t890/error.c (revision 6323) +++ src/southbridge/via/k8t890/error.c (working copy) @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007 Rudolf Marek <[email protected]> + * Copyright (C) 2011 Alexandru Gagniuc <[email protected]> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,9 +22,11 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <console/console.h> +#include "k8x8xx.h" static void error_enable(struct device *dev) { + print_debug(" K8x8xx: Enabling NB error reporting: "); /* * bit0 - Enable V-link parity error reporting in 0x50 bit0 (RWC) * bit6 - Parity Error/SERR# Report Through V-Link to SB @@ -31,7 +34,11 @@ */ pci_write_config8(dev, 0x58, 0x81); + print_debug("Done\n"); /* TODO: enable AGP errors reporting on K8M890 */ } static const struct device_operations error_ops = { @@ -42,9 +49,21 @@ .ops_pci = 0, }; -static const struct pci_driver northbridge_driver_t __pci_driver = { +static const struct pci_driver northbridge_driver_t800 __pci_driver = { .ops = &error_ops, .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T800_ERR, +}; + +static const struct pci_driver northbridge_driver_m800 __pci_driver = { + .ops = &error_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8M800_ERR, +}; + +static const struct pci_driver northbridge_driver_t890 __pci_driver = { + .ops = &error_ops, + .vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_K8T890CE_1, }; Index: src/southbridge/via/k8t890/bridge.c =================================================================== --- src/southbridge/via/k8t890/bridge.c (revision 6323) +++ src/southbridge/via/k8t890/bridge.c (working copy) @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007 Rudolf Marek <[email protected]> - * + * Copyright (C) 2011 Alexandru Gagniuc <[email protected]> * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -21,12 +21,13 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <console/console.h> -#include "k8t890.h" +#include "k8x8xx.h" static void bridge_enable(struct device *dev) { u8 tmp; - print_debug("B188 device dump\n"); + /* VIA recommends this, sorry no known info. */ writeback(dev, 0x40, 0x91); @@ -63,8 +64,12 @@ .ops_pci = 0, }; -static const struct pci_driver northbridge_driver __pci_driver = { +/* + * K8T890 and K8T800 both use device B188 as the bridge, so no need to + * add a separate driver + */ +static const struct pci_driver northbridge_driver_890 __pci_driver = { .ops = &bridge_ops, .vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_K8T890CE_BR,
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