attached is a patch to enable mmconf access on RS690.
This patch is required for the upcoming Siemens sitemp mainboard.
1. Overwrite read resources in src/southbridge/amd/rs690/ht.c
a. disable and hide BAR3 so pci_get_resource() doesn't touch.
b. add an mmconf resource
2. Overwrite set_resources so that it:
a. writes the mmconf resource base to the BAR3
b. disable writes and hide BAR3
c. find a not assigned resource in the K8 mmio and
setup base and limit with flag nonposted
3. Add the resource as reserved in add_mainboard_resources()
4. in the mainboard's acpi_tables.c
a. pass the mmconf base to the dsdt.
b. create a ACPI mcfg table
I've testet with Linux 2.6.12, Linux 2.6.26 and Windows XP SP3 + ATI X1200
driver,
Linux 2.6.26 comes up with the following messages:
[ 0.232014] PCI: MCFG configuration 0: base e0000000 segment 0 buses 0 - 31
[ 0.232014] PCI: MCFG area at e0000000 reserved in E820
[ 0.232014] PCI: Using MMCONFIG at e0000000 - e1ffffff
[ 0.232014] PCI: Using configuration type 1 for base access
lspci -xxxx shows me 4Kb ext config space for some devices.
Can somebody please comment on the patch ? Would be nice !
Signed-off-by: Josef Kellermann<[email protected]> <mailto://[email protected]>
Index: src/southbridge/amd/rs690/ht.c
===================================================================
--- src/southbridge/amd/rs690/ht.c (Revision 6331)
+++ src/southbridge/amd/rs690/ht.c (Arbeitskopie)
@@ -24,6 +24,96 @@
#include <device/pci_ops.h>
#include "rs690.h"
+#ifndef CONFIG_EXT_CONF_SUPPORT
+#define CONFIG_EXT_CONF_SUPPORT 0
+#endif
+
+extern unsigned long log2(unsigned long x);
+
+static void ht_dev_set_resources(device_t dev)
+{
+#if CONFIG_EXT_CONF_SUPPORT == 1
+ unsigned reg;
+ device_t k8_f1;
+ resource_t rbase, rend;
+ u32 base, limit;
+ struct resource *resource;
+
+ printk(BIOS_DEBUG,"%s %s\n", dev_path(dev), __func__);
+
+ resource = probe_resource(dev, 0x1C);
+ if (resource) {
+ set_nbmisc_enable_bits(dev, 0x0, 1 << 3, 0 << 3); // make bar3
visible
+ set_nbcfg_enable_bits(dev, 0x7C, 1 << 30, 1 << 30); /*
Enables writes to the BAR3 register. */
+ set_nbcfg_enable_bits(dev, 0x84, 7 << 16, 0 << 16); // program
bus range: 255 busses
+ pci_write_config32(dev, 0x1C, resource->base);
+ /* Enable MMCONFIG decoding. */
+ set_htiu_enable_bits(dev, 0x32, 1 << 28, 1 << 28); /*
PCIEMiscInit */
+ set_nbcfg_enable_bits(dev, 0x7C, 1 << 30, 0 << 30); /*
Disable writes to the BAR3 register. */
+ set_nbmisc_enable_bits(dev, 0x0, 1 << 3, 1 << 3); // hide bar 3
+
+ // setup resource nonposted in k8 mmio
+ /* Get the base address */
+ rbase = resource->base;
+ /* Get the limit (rounded up) */
+ rend = resource_end(resource);
+ printk(BIOS_DEBUG,"%s: %s[0x1C] base = %0llx limit = %0llx\n",
__func__, dev_path(dev), rbase, rend);
+ k8_f1 = dev_find_slot(0,PCI_DEVFN(0x18,1));
+ // find a not assigned resource
+ for( reg = 0xb8; reg >= 0x80; reg -= 8 ) {
+ base = pci_read_config32(k8_f1,reg);
+ limit = pci_read_config32(k8_f1,reg+4);
+ if( !(base & 3) ) break; // found a not assigned
resource
+ }
+ if( !(base & 3) ) {
+ u32 sblk;
+ device_t k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
+ /* Remember this resource has been stored. */
+ resource->flags |= IORESOURCE_STORED;
+ report_resource_stored(dev, resource, " <mmconfig>");
+ /* Get SBLink value (HyperTransport I/O Hub Link ID). */
+ sblk = (pci_read_config32(k8_f0, 0x64) >> 8) & 0x3;
+ base &= 0x000000f0;
+ base |= ((rbase >> 8) & 0xffffff00);
+ base |= 3;
+ limit &= 0x00000048;
+ limit |= ((rend >> 8) & 0xffffff00);
+ limit |= (sblk << 4);
+ limit |= (1 << 7);
+ printk(BIOS_INFO, "%s <- index %x base %04x limit
%04x\n", dev_path(k8_f1), reg, base, limit);
+ pci_write_config32(k8_f1, reg+4, limit);
+ pci_write_config32(k8_f1, reg, base);
+ }
+ }
+#endif
+ pci_dev_set_resources(dev);
+}
+
+static void ht_dev_read_resources(device_t dev)
+{
+#if CONFIG_EXT_CONF_SUPPORT == 1
+ struct resource *res;
+
+ printk(BIOS_DEBUG,"%s %s\n", dev_path(dev), __func__);
+ set_nbmisc_enable_bits(dev, 0x0, 1 << 3, 1 << 3); // hide bar 3
+#endif
+
+ pci_dev_read_resources(dev);
+
+#if CONFIG_EXT_CONF_SUPPORT == 1
+ /* Add an MMCONFIG resource. */
+ res = new_resource(dev, 0x1C);
+ res->base = CONFIG_EXT_CONF_BASE_ADDRESS;
+ res->size = CONFIG_EXT_CONF_BUS_NUMBER * 1024 * 1024;
+ res->align = log2(res->size);
+ res->gran = log2(res->size);
+ res->limit = 0xffffffffffffffffULL; /* 64bit */
+ res->flags = IORESOURCE_FIXED | IORESOURCE_MEM | IORESOURCE_PCI64 |
IORESOURCE_ASSIGNED;
+
+ compact_resources(dev);
+#endif
+}
+
/* for UMA internal graphics */
void avoid_lpc_dma_deadlock(device_t nb_dev, device_t sb_dev)
{
@@ -80,8 +170,8 @@
};
static struct device_operations ht_ops = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
+ .read_resources = ht_dev_read_resources,
+ .set_resources = ht_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = pcie_init,
.scan_bus = 0,
--
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