Author: oxygene
Date: Thu Feb 10 08:48:07 2011
New Revision: 6339
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6339

Log:
Fix a potential system hang by handling AMD Model F Erratum 89
a bit later.

Signed-off-by: Josef Kellermann <[email protected]>
Acked-by: Alexandru Gagniuc <[email protected]>

Modified:
   trunk/src/cpu/amd/model_fxx/model_fxx_init.c

Modified: trunk/src/cpu/amd/model_fxx/model_fxx_init.c
==============================================================================
--- trunk/src/cpu/amd/model_fxx/model_fxx_init.c        Tue Feb  8 17:07:49 
2011        (r6338)
+++ trunk/src/cpu/amd/model_fxx/model_fxx_init.c        Thu Feb 10 08:48:07 
2011        (r6339)
@@ -384,23 +384,6 @@
                wrmsr_amd(DC_CFG_MSR, msr);
 
        }
-       /* I can't touch this msr on early buggy cpus */
-       if (!is_cpu_pre_b3()) {
-
-               /* Erratum 89 ... */
-               msr = rdmsr(NB_CFG_MSR);
-               msr.lo |= 1 << 3;
-
-               if (!is_cpu_pre_c0() && is_cpu_pre_d0()) {
-                       /* D0 later don't need it */
-                       /* Erratum 86 Disable data masking on C0 and
-                        * later processor revs.
-                        * FIXME this is only needed if ECC is enabled.
-                        */
-                       msr.hi |= 1 << (36 - 32);
-               }
-               wrmsr(NB_CFG_MSR, msr);
-       }
 
        /* Erratum 97 ... */
        if (!is_cpu_pre_c0() && is_cpu_pre_d0()) {
@@ -445,7 +428,28 @@
                msr.hi |= 1;
                wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
        }
+       
+#if CONFIG_K8_REV_F_SUPPORT == 0
+               /* I can't touch this msr on early buggy cpus */
+       if (!is_cpu_pre_b3())
+#endif
+       {
 
+               /* Erratum 89 ... */
+               msr = rdmsr(NB_CFG_MSR);
+               msr.lo |= 1 << 3;
+#if CONFIG_K8_REV_F_SUPPORT == 0
+               if (!is_cpu_pre_c0() && is_cpu_pre_d0()) {
+                       /* D0 later don't need it */
+                       /* Erratum 86 Disable data masking on C0 and
+                        * later processor revs.
+                        * FIXME this is only needed if ECC is enabled.
+                        */
+                       msr.hi |= 1 << (36 - 32);
+               }
+#endif
+               wrmsr(NB_CFG_MSR, msr);
+       }
        /* Erratum 122 */
        msr = rdmsr(HWCR_MSR);
        msr.lo |= 1 << 6;

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