removed /* LPC DMA Deadlock workaround? */ ...

setting bit#21 in k8_f0#68 is part of the errata#169 which is handled in amdk8/coherent.c

see patch for details.

Signed-off-by: Josef Kellermann <[email protected]> <mailto://[email protected]>

diff --git a/src/southbridge/amd/rs690/gfx.c b/src/southbridge/amd/rs690/gfx.c
index 175ea71..0308ce4 100644
--- a/src/southbridge/amd/rs690/gfx.c
+++ b/src/southbridge/amd/rs690/gfx.c
@@ -114,7 +114,7 @@ static void rs690_internal_gfx_enable(device_t dev)
 {
        u32 l_dword;
        int i;
-       device_t k8_f0 = 0, k8_f2 = 0;
+       device_t k8_f2 = 0;
        device_t nb_dev = dev_find_slot(0, 0);
 
        printk(BIOS_INFO, "rs690_internal_gfx_enable dev=0x%p, nb_dev=0x%p.\n", 
dev,
@@ -129,13 +129,6 @@ static void rs690_internal_gfx_enable(device_t dev)
        /* set TOM */
        rs690_set_tom(nb_dev);
 
-       /* LPC DMA Deadlock workaround? */
-       k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
-       l_dword = pci_read_config32(k8_f0, 0x68);
-       l_dword &= ~(1 << 22);
-       l_dword |= (1 << 21);
-       pci_write_config32(k8_f0, 0x68, l_dword);
-
        /* Enable 64bit mode. */
        set_nbmc_enable_bits(nb_dev, 0x5f, 0, 1 << 9);
        set_nbmc_enable_bits(nb_dev, 0xb0, 0, 1 << 8);
-- 
coreboot mailing list: [email protected]
http://www.coreboot.org/mailman/listinfo/coreboot

Reply via email to