see patch
Improving BKDG implementation of P-states, CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode. bits 13 - 15 of F3xd4 (StutterScrubEn, CacheFlushImmOnAllHalt and MTC1eEn are reserved for revisions D0 and earlier, so whe should not set them to 0 in fidvid.c config_clk_power_ctrl_reg0(...), called from prep_fid_change. For revisions > D0 (when we support them) it is ok not ot clear them, because they are documented as 0 on reset. bit 12 should be left alone according to BKDG. Should I set 11:8 ClkRampHystSel to 0 in the mask too, just to indicate we're touching them ? We'll OR them to 1111 anyway... Signed-off-by: Xavi Drudis Ferran <[email protected]> --- src/northbridge/amd/amdht/AsPsDefs.h 2011-02-15 23:05:01.000000000 +0100 +++ src/northbridge/amd/amdht/AsPsDefs.h 2011-02-15 01:23:46.000000000 +0100 @@ -111,7 +111,7 @@ #define STC_PS_LMT_MASK 0x8fffffff /* StcPstateLimit mask off */ #define CPTC0 0x0d4 /* Clock Power/Timing Control0 Register*/ -#define CPTC0_MASK 0x000c0fff /* Reset mask for this register */ +#define CPTC0_MASK 0x000cffff /* Reset mask for this register */ #define CPTC0_NBFID_MASK 0xffffffe0 /* NbFid mask off for this register */ #define CPTC0_NBFID_MON 0x1f /* NbFid mask on for this register */ #define NB_FID_EN 0x20 /* NbFidEn bit ON */
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