Attached patch adds sane compile-time defaults via Kconfig options for
CMOS options
'iommu, ECC_memory, max_mem_clock, hw_scrubber, interleave_chip_selects'.
Avoid build error if any of these CMOS options are not defined.
Checks the return value of 'get_option(..)', if not done yet, and
if CMOS option not exist grab a Kconfig option otherwise a hardcoded
value is used.
Signed-off-by: Josef Kellermann <[email protected]> <mailto://[email protected]>
>From 7442dfd6d12bf596fdb64bff370631eb2e75c542 Mon Sep 17 00:00:00 2001
From: Josef Kellermann <[email protected]>
Date: Fri, 18 Feb 2011 14:25:33 +0100
Subject: [PATCH 2/2] This patch
adds sane compile-time defaults via Kconfig options for CMOS options
'iommu, ECC_memory, max_mem_clock, hw_scrubber, interleave_chip_selcts'.
avoid build error if any of these CMOS options are not defined.
checks the return value of 'get_option(..)', if not done yet, and
if CMOS option not exist grab a Kconfig option otherwise a hardcoded
value is used.
---
src/cpu/amd/model_fxx/model_fxx_init.c | 12 +++++++--
src/northbridge/amd/amdk8/misc_control.c | 9 +++++-
src/northbridge/amd/amdk8/raminit_f.c | 37 +++++++++++++++++++++++------
3 files changed, 45 insertions(+), 13 deletions(-)
diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c
b/src/cpu/amd/model_fxx/model_fxx_init.c
index a5112b3..bfdefa2 100644
--- a/src/cpu/amd/model_fxx/model_fxx_init.c
+++ b/src/cpu/amd/model_fxx/model_fxx_init.c
@@ -263,8 +263,15 @@ static void init_ecc_memory(unsigned node_id)
}
/* See if we scrubbing should be enabled */
- enable_scrubbing = 1;
- get_option(&enable_scrubbing, "hw_scrubber");
+ /* fixme: does it make any sense enabling scrubbing if not ECC_memory ?
*/
+ dcl = pci_read_config32(f2_dev, DRAM_CONFIG_LOW);
+ enable_scrubbing = (dcl & DCL_DimmEccEn) ? 1 : 0; /* default: enable
scrubbing if ECC_memory */
+ if( get_option(&enable_scrubbing, "hw_scrubber") < 0 )
+ {
+#if defined(CONFIG_HW_SCRUBBER)
+ enable_scrubbing = CONFIG_HW_SCRUBBER;
+#endif
+ }
/* Enable cache scrubbing at the lowest possible rate */
if (enable_scrubbing) {
@@ -279,7 +286,6 @@ static void init_ecc_memory(unsigned node_id)
}
/* If ecc support is not enabled don't touch memory */
- dcl = pci_read_config32(f2_dev, DRAM_CONFIG_LOW);
if (!(dcl & DCL_DimmEccEn)) {
printk(BIOS_DEBUG, "ECC Disabled\n");
return;
diff --git a/src/northbridge/amd/amdk8/misc_control.c
b/src/northbridge/amd/amdk8/misc_control.c
index fa90a55..e65b2a9 100644
--- a/src/northbridge/amd/amdk8/misc_control.c
+++ b/src/northbridge/amd/amdk8/misc_control.c
@@ -46,9 +46,14 @@ static void mcf3_read_resources(device_t dev)
if (dev->path.pci.devfn != PCI_DEVFN(0x18, 3)) {
return;
}
-
+
iommu = 1;
- get_option(&iommu, "iommu");
+ if( get_option(&iommu, "iommu") < 0 )
+ {
+#if defined(CONFIG_IOMMU)
+ iommu = CONFIG_IOMMU;
+#endif
+ }
if (iommu) {
/* Add a GART aperture resource */
diff --git a/src/northbridge/amd/amdk8/raminit_f.c
b/src/northbridge/amd/amdk8/raminit_f.c
index 3135bce..d7d6157 100644
--- a/src/northbridge/amd/amdk8/raminit_f.c
+++ b/src/northbridge/amd/amdk8/raminit_f.c
@@ -1107,6 +1107,15 @@ static unsigned long interleave_chip_selects(const
struct mem_controller *ctrl,
/* See if all of the memory chip selects are the same size
* and if so count them.
*/
+#if defined(CMOS_VSTART_interleave_chip_selects)
+ if (read_option(CMOS_VSTART_interleave_chip_selects,
CMOS_VLEN_interleave_chip_selects, 1) == 0)
+ return 0;
+#else
+#if !defined(CONFIG_INTERLEAVE_CHIP_SELECTS) ||
(CONFIG_INTERLEAVE_CHIP_SELECTS == 0)
+ return 0;
+#endif
+#endif
+
chip_selects = 0;
common_size = 0;
common_cs_mode = 0xff;
@@ -1279,15 +1288,10 @@ static void order_dimms(const struct mem_controller
*ctrl,
{
unsigned long tom_k, base_k;
- if (read_option(CMOS_VSTART_interleave_chip_selects,
- CMOS_VLEN_interleave_chip_selects, 1) != 0) {
- tom_k = interleave_chip_selects(ctrl, meminfo->is_Width128);
- } else {
- printk(BIOS_DEBUG, "Interleaving disabled\n");
- tom_k = 0;
- }
+ tom_k = interleave_chip_selects(ctrl, meminfo->is_Width128);
if (!tom_k) {
+ printk(BIOS_DEBUG, "Interleaving disabled\n");
tom_k = order_chip_selects(ctrl);
}
@@ -1801,7 +1805,17 @@ static struct spd_set_memclk_result spd_set_memclk(const
struct mem_controller *
value = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) &
NBCAP_MEMCLK_MASK];
bios_cycle_time = min_cycle_times[
- read_option(CMOS_VSTART_max_mem_clock, CMOS_VLEN_max_mem_clock,
0)];
+#ifdef CMOS_VSTART_max_mem_clock
+ read_option(CMOS_VSTART_max_mem_clock, CMOS_VLEN_max_mem_clock,
0)
+#else
+#if defined(CONFIG_MAX_MEM_CLOCK)
+ CONFIG_MAX_MEM_CLOCK
+#else
+ 0 // use DDR400 as default
+#endif
+#endif
+ ];
+
if (bios_cycle_time > min_cycle_time) {
min_cycle_time = bios_cycle_time;
}
@@ -2360,14 +2374,21 @@ static void set_ecc(const struct mem_controller *ctrl,
if (nbcap & NBCAP_ECC) {
dcl |= DCL_DimmEccEn;
}
+#ifdef CMOS_VSTART_ECC_memory
if (read_option(CMOS_VSTART_ECC_memory, CMOS_VLEN_ECC_memory, 1) == 0) {
dcl &= ~DCL_DimmEccEn;
}
+#else // CMOS_VSTART_ECC_memory not defined
+#if defined(CONFIG_ECC_MEMORY) && (CONFIG_ECC_MEMORY == 0)
+ dcl &= ~DCL_DimmEccEn;
+#endif
+#endif
pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
meminfo->is_ecc = 1;
if (!(dcl & DCL_DimmEccEn)) {
meminfo->is_ecc = 0;
+ printk(BIOS_DEBUG, "set_ecc: ECC disabled\n");
return; // already disabled the ECC, so don't need to read SPD
any more
}
--
1.7.1
--
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