Author: oxygene Date: Thu Feb 24 15:35:42 2011 New Revision: 6380 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6380
Log: Add compile-time defaults to some K8 CMOS options in case they're absent in CMOS This affects the CMOS options iommu, ECC_memory, max_mem_clock, hw_scrubber, interleave_chip_selects. If they're absent in cmos.layout, a Kconfig value is used if it exists, or a hardcoded default otherwise. [Patrick: I changed the ramstage CMOS handling a bit, and dropped the reliance of hw_scrubber on ECC RAM, as it has nothing to do with it - it's the cache that's being scrubbed here.] Signed-off-by: Josef Kellermann <[email protected]> Acked-by: Patrick Georgi <[email protected]> Modified: trunk/src/cpu/amd/model_fxx/Kconfig trunk/src/cpu/amd/model_fxx/model_fxx_init.c trunk/src/northbridge/amd/amdk8/Kconfig trunk/src/northbridge/amd/amdk8/misc_control.c trunk/src/northbridge/amd/amdk8/raminit_f.c Modified: trunk/src/cpu/amd/model_fxx/Kconfig ============================================================================== --- trunk/src/cpu/amd/model_fxx/Kconfig Thu Feb 24 14:54:10 2011 (r6379) +++ trunk/src/cpu/amd/model_fxx/Kconfig Thu Feb 24 15:35:42 2011 (r6380) @@ -14,6 +14,10 @@ default n default y if K8_REV_F_SUPPORT +config HW_SCRUBBER + bool + default n + if SET_FIDVID config SET_FIDVID_DEBUG bool Modified: trunk/src/cpu/amd/model_fxx/model_fxx_init.c ============================================================================== --- trunk/src/cpu/amd/model_fxx/model_fxx_init.c Thu Feb 24 14:54:10 2011 (r6379) +++ trunk/src/cpu/amd/model_fxx/model_fxx_init.c Thu Feb 24 15:35:42 2011 (r6380) @@ -264,7 +264,10 @@ /* See if we scrubbing should be enabled */ enable_scrubbing = 1; - get_option(&enable_scrubbing, "hw_scrubber"); + if( get_option(&enable_scrubbing, "hw_scrubber") < 0 ) + { + enable_scrubbing = CONFIG_HW_SCRUBBER; + } /* Enable cache scrubbing at the lowest possible rate */ if (enable_scrubbing) { Modified: trunk/src/northbridge/amd/amdk8/Kconfig ============================================================================== --- trunk/src/northbridge/amd/amdk8/Kconfig Thu Feb 24 14:54:10 2011 (r6379) +++ trunk/src/northbridge/amd/amdk8/Kconfig Thu Feb 24 15:35:42 2011 (r6380) @@ -83,6 +83,10 @@ endif #K8_REV_F_SUPPORT +config IOMMU + bool + default y + endif #NORTHBRIDGE_AMD_K8 source src/northbridge/amd/amdk8/root_complex/Kconfig Modified: trunk/src/northbridge/amd/amdk8/misc_control.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/misc_control.c Thu Feb 24 14:54:10 2011 (r6379) +++ trunk/src/northbridge/amd/amdk8/misc_control.c Thu Feb 24 15:35:42 2011 (r6380) @@ -48,7 +48,10 @@ } iommu = 1; - get_option(&iommu, "iommu"); + if( get_option(&iommu, "iommu") < 0 ) + { + iommu = CONFIG_IOMMU; + } if (iommu) { /* Add a GART aperture resource */ Modified: trunk/src/northbridge/amd/amdk8/raminit_f.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/raminit_f.c Thu Feb 24 14:54:10 2011 (r6379) +++ trunk/src/northbridge/amd/amdk8/raminit_f.c Thu Feb 24 15:35:42 2011 (r6380) @@ -1107,6 +1107,15 @@ /* See if all of the memory chip selects are the same size * and if so count them. */ +#if defined(CMOS_VSTART_interleave_chip_selects) + if (read_option(CMOS_VSTART_interleave_chip_selects, CMOS_VLEN_interleave_chip_selects, 1) == 0) + return 0; +#else +#if !defined(CONFIG_INTERLEAVE_CHIP_SELECTS) || (CONFIG_INTERLEAVE_CHIP_SELECTS == 0) + return 0; +#endif +#endif + chip_selects = 0; common_size = 0; common_cs_mode = 0xff; @@ -1279,15 +1288,10 @@ { unsigned long tom_k, base_k; - if (read_option(CMOS_VSTART_interleave_chip_selects, - CMOS_VLEN_interleave_chip_selects, 1) != 0) { - tom_k = interleave_chip_selects(ctrl, meminfo->is_Width128); - } else { - printk(BIOS_DEBUG, "Interleaving disabled\n"); - tom_k = 0; - } + tom_k = interleave_chip_selects(ctrl, meminfo->is_Width128); if (!tom_k) { + printk(BIOS_DEBUG, "Interleaving disabled\n"); tom_k = order_chip_selects(ctrl); } @@ -1801,7 +1805,17 @@ value = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP); min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK]; bios_cycle_time = min_cycle_times[ - read_option(CMOS_VSTART_max_mem_clock, CMOS_VLEN_max_mem_clock, 0)]; +#ifdef CMOS_VSTART_max_mem_clock + read_option(CMOS_VSTART_max_mem_clock, CMOS_VLEN_max_mem_clock, 0) +#else +#if defined(CONFIG_MAX_MEM_CLOCK) + CONFIG_MAX_MEM_CLOCK +#else + 0 // use DDR400 as default +#endif +#endif + ]; + if (bios_cycle_time > min_cycle_time) { min_cycle_time = bios_cycle_time; } @@ -2360,14 +2374,21 @@ if (nbcap & NBCAP_ECC) { dcl |= DCL_DimmEccEn; } +#ifdef CMOS_VSTART_ECC_memory if (read_option(CMOS_VSTART_ECC_memory, CMOS_VLEN_ECC_memory, 1) == 0) { dcl &= ~DCL_DimmEccEn; } +#else // CMOS_VSTART_ECC_memory not defined +#if defined(CONFIG_ECC_MEMORY) && (CONFIG_ECC_MEMORY == 0) + dcl &= ~DCL_DimmEccEn; +#endif +#endif pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl); meminfo->is_ecc = 1; if (!(dcl & DCL_DimmEccEn)) { meminfo->is_ecc = 0; + printk(BIOS_DEBUG, "set_ecc: ECC disabled\n"); return; // already disabled the ECC, so don't need to read SPD any more } -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
