Dear coreboot readers! This is the automatic build system of coreboot.
The developer "mjones" checked in revision 6401 to the coreboot repository. This caused the following changes: Change Log: Improving BKDG implementation of P-states, CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode. Factor out some common expressions. Add an error message when coreboots hangs waiting for a pstate that never comes (it happened to me), and throw some paranoia at it for good mesure. If I understood BKDG fam10 CPUs never need a software initiated vid transition, because the hardware knows what to do when you just request a Pstate change if the cpu is properly configured. In fact unifying a little what PVI and SVI do was better for my board (SVI). So I drop transitionVid, which I didn't understand either (why did it have a case for PVI if it is never called for PVI ? Why did the PVI case distinguigh cpu or nb when PVI is theoretically single voltage plane ? ). Signed-off-by: Xavi Drudis Ferran <[email protected]> Acked-by: Marc Jones <[email protected]> Build Log: Compilation of amd:bimini_fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6401&device=bimini_fam10&vendor=amd&num=2 Compilation of amd:tilapia_fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6401&device=tilapia_fam10&vendor=amd&num=2 Compilation of gigabyte:ma785gmt has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6401&device=ma785gmt&vendor=gigabyte&num=2 If something broke during this checkin please be a pain in mjones's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
