On 3/1/11 5:47 PM, zxy__1127 wrote: > *发 件人：* Keith Hui > *发 送时间：* 2011-03-02 00:32:50 > *收 件人：* [email protected] > *抄 送：* > *主 题：* Re: [coreboot] how to deal with large romstage size? > > Hi all, > > > > After I add some memory initialisize code, the romstage is over 64K > byte,and tne code can't run properly. > > Then what should I do when romstage is over 64K byte? Is romstage's > size limits to 64KB? > > > > Thanks a lot! > > 2011-03-01 > > > It is not a direct limitation on romstage's size, but a result of most > chipsets mapping only the top 64KB of flash to the memory space. Most > chipsets require some programming to have the entire flash rom appear > in memory. Your code didn't run properly because not all of it has > been mapped to memory space and get effectively cut. > But my romstage for Intel 440BX is only about 11KB. What chipset are > you dealing with? > my chipset is intel arrandal+qm57,it's MRC code is very large(about > 110KB after build) :-( > Also, look at implementing TINY_BOOTBLOCK which leaves a tiny stub, > well within the 64KB limit, which does nothing but enable enough > hardware (southbridge to be exact) to make the entire rom visible, > then locates and executes the real romstage which is now just another > stage in CBFS. Again, all 440BX/PIIX4 boards implement this and can be > a reference. > *actually, it can run at bootblock,but can not reach "cache_as_ram:".* >
I think you need to make the complete flash visible in a southbridge bootblock.c It would help if you could publish your current code so we can do better than asking the crystal ball for answers ;) Stefan
-- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
