While the previous two patches were innocently trivial and abuild tested, this one _will_ break the build for several Socket 604 boards. We want the build to be broken until we can port those to CAR.
See patch for verbosity.
The Tyan s2735 is a Socket 604 board that uses CAR. cache_as_ram.inc is included specifically for this board in src/arch/x86/Makefile.inc . This patch makes the option generic to all Socket 604 boards. Expect the build for the following boards to be broken by this patch: dell/s1850 intel/jarrell intel/xe7501devkit supermicro/x6dai_g supermicro/x6dhe_g supermicro/x6dhe_g2 supermicro/x6dhr_ig supermicro/x6dhr_ig2 These boards need to be individually ported to CAR. The job is as simple as removing "select ROMCC" from each board's Kconfig and fixing the build errors that appear. Signed-off-by: Alexandru Gagniuc <[email protected]> Index: src/mainboard/tyan/s2735/Kconfig =================================================================== --- src/mainboard/tyan/s2735/Kconfig (revision 6429) +++ src/mainboard/tyan/s2735/Kconfig (working copy) @@ -13,7 +13,6 @@ select HAVE_MP_TABLE select UDELAY_TSC select HAVE_OPTION_TABLE - select CACHE_AS_RAM select USE_WATCHDOG_ON_BOOT select BOARD_ROMSIZE_KB_512 Index: src/cpu/intel/socket_mPGA604/Kconfig =================================================================== --- src/cpu/intel/socket_mPGA604/Kconfig (revision 6429) +++ src/cpu/intel/socket_mPGA604/Kconfig (working copy) @@ -1,3 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 Alexandru Gagniuc <[email protected]> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + config CPU_INTEL_SOCKET_MPGA604 bool select CPU_INTEL_MODEL_F2X @@ -6,6 +26,7 @@ select MMX select SSE select UDELAY_TSC + select CACHE_AS_RAM # mPGA604 are usually Intel Netburst CPUs which should have SSE2 # but the ramtest.c code on the Dell S1850 seems to choke on @@ -14,3 +35,8 @@ bool default n depends on CPU_INTEL_SOCKET_MPGA604 + +# We need to specify this in order for cache_as_ram.inc to assemble +config DCACHE_RAM_SIZE + hex + default 0x1000 Index: src/cpu/intel/socket_mPGA604/Makefile.inc =================================================================== --- src/cpu/intel/socket_mPGA604/Makefile.inc (revision 6429) +++ src/cpu/intel/socket_mPGA604/Makefile.inc (working copy) @@ -1,3 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 Alexandru Gagniuc <[email protected]> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + ramstage-y += socket_mPGA604.c subdirs-y += ../model_f2x subdirs-y += ../model_f3x @@ -10,3 +30,5 @@ subdirs-y += ../microcode subdirs-y += ../hyperthreading +# This is a CAR capable socket god damn it!!! +cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc Index: src/arch/x86/Makefile.inc =================================================================== --- src/arch/x86/Makefile.inc (revision 6429) +++ src/arch/x86/Makefile.inc (working copy) @@ -186,13 +186,6 @@ crt0s += $(cpu_incs) -# -# FIXME move to CPU_INTEL_SOCKET_MPGA604 -# -ifeq ($(CONFIG_BOARD_TYAN_S2735),y) -crt0s += $(src)/cpu/intel/car/cache_as_ram.inc -endif - ifeq ($(CONFIG_LLSHELL),y) crt0s += $(src)/arch/x86/llshell/llshell.inc endif
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