On Fri, Mar 11, 2011 at 05:49:50PM +0200, Alex G. wrote: > > 1. Does Coreboot work with Phenom II Thuban CPU ? I want 6-core CPU of > > Phenom2 > > > It's supported. >
I didn't know this had been tested. It's a little difficult for me to keep track of all mail in the list. http://www.coreboot.org/Supported_Chipsets_and_Devices says [only?] FAM10 revisions B0-B3 are supported. My Phenom II X4 910e is rev RB_C3 and still doesn't boot (although I no longer think it's the CPU but the southbridge, I can't confirm either until I can boot). According to http://en.wikipedia.org/wiki/List_of_AMD_Phenom_microprocessors#Phenom_series all Phenom II X6 would be revision E0 (one could look at more authoritative sources, maybe) In theory many revisions should work. In practice there are some constants in src/northbridge/amd/amdmct/amddefs.h which allocate one bit in a 32 bit value for each revision. Then these are used to build masks to test whether to apply workarounds for CPU errata or particular initializations (like in src/cpu/amd/model_10xxx/defaults.h). Some revisions (beyond HY_D0, I think), don't fit in these 32 bits. I suspect those revisions may not work, but maybe these revisions might work because they just don't need workarounds, etc. I even sent some patches that would only make sense for revision E and they were committed, but I couldn't test them (I sent them precisely because I thought no revision E CPU had been used with coreboot, so I couldn't break anything that worked before, just hopefully add a small part to support future work). It might be good to collect a list of tested CPU revisions and maybe any issues found or any tests performed, if the supported chipsets page is out of date for FAM10. I'm sorry I can't contribute to this list though, until my board boots. P.S. Whether E0 works or not, there's good documentation for it, so it is fixable. -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
