Author: zbao Date: Mon Mar 28 06:38:14 2011 New Revision: 6466 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6466
Log: Add support for Supermicro H8scm. It is AMD C32 + SR5650 + SP5100. It is created by svn copy amd/tilapia_fam10. Signed-off-by: Zheng Bao <[email protected]> Acked-by: Marc Jones <[email protected]> Added: trunk/src/mainboard/supermicro/h8scm_fam10/ (props changed) - copied from r6459, trunk/src/mainboard/amd/tilapia_fam10/ Modified: trunk/src/mainboard/supermicro/Kconfig trunk/src/mainboard/supermicro/h8scm_fam10/Kconfig trunk/src/mainboard/supermicro/h8scm_fam10/acpi/routing.asl trunk/src/mainboard/supermicro/h8scm_fam10/acpi_tables.c trunk/src/mainboard/supermicro/h8scm_fam10/devicetree.cb trunk/src/mainboard/supermicro/h8scm_fam10/dsdt.asl trunk/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c trunk/src/mainboard/supermicro/h8scm_fam10/irq_tables.c trunk/src/mainboard/supermicro/h8scm_fam10/mainboard.c trunk/src/mainboard/supermicro/h8scm_fam10/mptable.c trunk/src/mainboard/supermicro/h8scm_fam10/romstage.c Modified: trunk/src/mainboard/supermicro/Kconfig ============================================================================== --- trunk/src/mainboard/supermicro/Kconfig Mon Mar 28 06:36:21 2011 (r6465) +++ trunk/src/mainboard/supermicro/Kconfig Mon Mar 28 06:38:14 2011 (r6466) @@ -11,6 +11,8 @@ bool "H8DMR-i2 (Fam10)" config BOARD_SUPERMICRO_H8QME_FAM10 bool "H8QME-2+ (Fam10)" +config BOARD_SUPERMICRO_H8SCM_FAM10 + bool "H8SCM (Fam10)" config BOARD_SUPERMICRO_X6DAI_G bool "X6DAi-G" config BOARD_SUPERMICRO_X6DHE_G2 @@ -28,6 +30,7 @@ source "src/mainboard/supermicro/h8dmr/Kconfig" source "src/mainboard/supermicro/h8dmr_fam10/Kconfig" source "src/mainboard/supermicro/h8qme_fam10/Kconfig" +source "src/mainboard/supermicro/h8scm_fam10/Kconfig" source "src/mainboard/supermicro/x6dai_g/Kconfig" source "src/mainboard/supermicro/x6dhe_g2/Kconfig" source "src/mainboard/supermicro/x6dhe_g/Kconfig" Modified: trunk/src/mainboard/supermicro/h8scm_fam10/Kconfig ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/Kconfig Tue Mar 22 14:40:09 2011 (r6459) +++ trunk/src/mainboard/supermicro/h8scm_fam10/Kconfig Mon Mar 28 06:38:14 2011 (r6466) @@ -1,35 +1,34 @@ -if BOARD_AMD_TILAPIA_FAM10 +if BOARD_SUPERMICRO_H8SCM_FAM10 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 - select CPU_AMD_SOCKET_AM3 + select CPU_AMD_SOCKET_C32 select DIMM_DDR3 select DIMM_REGISTERED select NORTHBRIDGE_AMD_AMDFAM10 - select SOUTHBRIDGE_AMD_RS780 - select SOUTHBRIDGE_AMD_SB700 - select SUPERIO_ITE_IT8718F + select SOUTHBRIDGE_AMD_SR5650 + select SOUTHBRIDGE_AMD_SP5100 + select SUPERIO_WINBOND_W83627HF select HAVE_BUS_CONFIG select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE + select GENERATE_PIRQ_TABLE + select GENERATE_MP_TABLE select HAVE_MAINBOARD_RESOURCES select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT select AMDMCT - select HAVE_ACPI_TABLES - select BOARD_ROMSIZE_KB_1024 + select GENERATE_ACPI_TABLES + select BOARD_ROMSIZE_KB_2048 select RAMINIT_SYSINFO select ENABLE_APIC_EXT_ID select GFXUMA - select QRANK_DIMM_SUPPORT config MAINBOARD_DIR string - default amd/tilapia_fam10 + default supermicro/h8scm_fam10 config APIC_ID_OFFSET hex @@ -37,15 +36,15 @@ config MAINBOARD_PART_NUMBER string - default "Tilapia (Fam10)" + default "H8SCM (Fam10)" config MAX_CPUS int - default 8 + default 16 config MAX_PHYSICAL_CPUS int - default 2 + default 1 config MEM_TRAIN_SEQ int @@ -69,7 +68,7 @@ config AMD_UCODE_PATCH_FILE string - default "mc_patch_010000b6.h" + default "mc_patch_010000c4.h" config RAMTOP hex @@ -79,8 +78,12 @@ hex default 0xc0000 +config ACPI_SSDTX_NUM + int + default 0 + config RAMBASE hex default 0x200000 -endif # BOARD_AMD_TILAPIA_FAM10 +endif # BOARD_AMD_H8SCM_FAM10 Modified: trunk/src/mainboard/supermicro/h8scm_fam10/acpi/routing.asl ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/acpi/routing.asl Tue Mar 22 14:40:09 2011 (r6459) +++ trunk/src/mainboard/supermicro/h8scm_fam10/acpi/routing.asl Mon Mar 28 06:38:14 2011 (r6466) @@ -30,6 +30,8 @@ Name(PR0, Package(){ /* NB devices */ /* Bus 0, Dev 0 - RS780 Host Controller */ + Package (0x04) { 0xFFFF, Zero, INTA, Zero }, + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ Package(){0x0002FFFF, 0, INTC, 0 }, @@ -37,16 +39,20 @@ Package(){0x0002FFFF, 2, INTA, 0 }, Package(){0x0002FFFF, 3, INTB, 0 }, /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ + Package(){0x0003FFFF, 0, INTD, 0 }, + Package(){0x0003FFFF, 1, INTA, 0 }, + Package(){0x0003FFFF, 2, INTB, 0 }, + Package(){0x0003FFFF, 3, INTC, 0 }, /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ Package(){0x0004FFFF, 0, INTA, 0 }, Package(){0x0004FFFF, 1, INTB, 0 }, Package(){0x0004FFFF, 2, INTC, 0 }, Package(){0x0004FFFF, 3, INTD, 0 }, /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - /* Package(){0x0005FFFF, 0, INTB, 0 }, */ - /* Package(){0x0005FFFF, 1, INTC, 0 }, */ - /* Package(){0x0005FFFF, 2, INTD, 0 }, */ - /* Package(){0x0005FFFF, 3, INTA, 0 }, */ + Package(){0x0005FFFF, 0, INTB, 0 }, + Package(){0x0005FFFF, 1, INTC, 0 }, + Package(){0x0005FFFF, 2, INTD, 0 }, + Package(){0x0005FFFF, 3, INTA, 0 }, /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ Package(){0x0006FFFF, 0, INTC, 0 }, Package(){0x0006FFFF, 1, INTD, 0 }, @@ -59,17 +65,43 @@ Package(){0x0007FFFF, 3, INTC, 0 }, /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ - /* SB devices */ - /* Bus 0, Dev 17 - SATA controller #2 */ - /* Bus 0, Dev 18 - SATA controller #1 */ - Package(){0x0011FFFF, 1, INTA, 0 }, + /* Bus 0, Dev 9 - PCIe Bridge for network card */ + Package(){0x0009FFFF, 0, INTB, 0 }, + Package(){0x0009FFFF, 1, INTC, 0 }, + Package(){0x0009FFFF, 2, INTD, 0 }, + Package(){0x0009FFFF, 3, INTA, 0 }, + + /* Bus 0, Dev a - PCIe Bridge for network card */ + Package(){0x000AFFFF, 0, INTC, 0 }, + Package(){0x000AFFFF, 1, INTD, 0 }, + Package(){0x000AFFFF, 2, INTA, 0 }, + Package(){0x000AFFFF, 3, INTB, 0 }, + + /* Bus 0, Dev b - */ + Package(){0x000BFFFF, 0, INTD, 0 }, + Package(){0x000BFFFF, 1, INTA, 0 }, + Package(){0x000BFFFF, 2, INTB, 0 }, + Package(){0x000BFFFF, 3, INTC, 0 }, + + /* Bus 0, Dev c - */ + Package(){0x000CFFFF, 0, INTA, 0 }, + Package(){0x000CFFFF, 1, INTB, 0 }, + Package(){0x000CFFFF, 2, INTC, 0 }, + Package(){0x000CFFFF, 3, INTD, 0 }, + + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, INTG, 0 }, /* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */ Package(){0x0012FFFF, 0, INTA, 0 }, Package(){0x0012FFFF, 1, INTB, 0 }, - Package(){0x0013FFFF, 0, INTA, 0 }, - Package(){0x0013FFFF, 1, INTB, 0 }, - Package(){0x0014FFFF, 2, INTA, 0 }, + Package(){0x0012FFFF, 2, INTC, 0 }, + Package(){0x0012FFFF, 3, INTD, 0 }, + + Package(){0x0013FFFF, 0, INTC, 0 }, + Package(){0x0013FFFF, 1, INTD, 0 }, + Package(){0x0013FFFF, 2, INTA, 0 }, + Package(){0x0013FFFF, 3, INTB, 0 }, /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:AC97 Audio;F6:AC97 Modem */ Package(){0x0014FFFF, 0, INTA, 0 }, @@ -81,71 +113,89 @@ Name(APR0, Package(){ /* NB devices in APIC mode */ /* Bus 0, Dev 0 - RS780 Host Controller */ + Package (0x04) { 0xFFFF, Zero, Zero, 16 }, /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ - /* Package(){0x0001FFFF, 0, 0, 18 }, */ - /* package(){0x0001FFFF, 1, 0, 19 }, */ /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ Package(){0x0002FFFF, 0, 0, 18 }, - /* Package(){0x0002FFFF, 1, 0, 19 }, */ - /* Package(){0x0002FFFF, 2, 0, 16 }, */ - /* Package(){0x0002FFFF, 3, 0, 17 }, */ + Package(){0x0002FFFF, 1, 0, 19 }, + Package(){0x0002FFFF, 2, 0, 16 }, + Package(){0x0002FFFF, 3, 0, 17 }, /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ Package(){0x0003FFFF, 0, 0, 19 }, + Package(){0x0003FFFF, 1, 0, 16 }, + Package(){0x0003FFFF, 2, 0, 17 }, + Package(){0x0003FFFF, 3, 0, 18 }, /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ Package(){0x0004FFFF, 0, 0, 16 }, - /* Package(){0x0004FFFF, 1, 0, 17 }, */ - /* Package(){0x0004FFFF, 2, 0, 18 }, */ - /* Package(){0x0004FFFF, 3, 0, 19 }, */ + Package(){0x0004FFFF, 1, 0, 17 }, + Package(){0x0004FFFF, 2, 0, 18 }, + Package(){0x0004FFFF, 3, 0, 19 }, /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - /* Package(){0x0005FFFF, 0, 0, 17 }, */ - /* Package(){0x0005FFFF, 1, 0, 18 }, */ - /* Package(){0x0005FFFF, 2, 0, 19 }, */ - /* Package(){0x0005FFFF, 3, 0, 16 }, */ + Package(){0x0005FFFF, 0, 0, 17 }, + Package(){0x0005FFFF, 1, 0, 18 }, + Package(){0x0005FFFF, 2, 0, 19 }, + Package(){0x0005FFFF, 3, 0, 16 }, /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ - /* Package(){0x0006FFFF, 0, 0, 18 }, */ - /* Package(){0x0006FFFF, 1, 0, 19 }, */ - /* Package(){0x0006FFFF, 2, 0, 16 }, */ - /* Package(){0x0006FFFF, 3, 0, 17 }, */ + Package(){0x0006FFFF, 0, 0, 18 }, + Package(){0x0006FFFF, 1, 0, 19 }, + Package(){0x0006FFFF, 2, 0, 16 }, + Package(){0x0006FFFF, 3, 0, 17 }, /* Bus 0, Dev 7 - PCIe Bridge for network card */ - /* Package(){0x0007FFFF, 0, 0, 19 }, */ - /* Package(){0x0007FFFF, 1, 0, 16 }, */ - /* Package(){0x0007FFFF, 2, 0, 17 }, */ - /* Package(){0x0007FFFF, 3, 0, 18 }, */ + Package(){0x0007FFFF, 0, 0, 19 }, + Package(){0x0007FFFF, 1, 0, 16 }, + Package(){0x0007FFFF, 2, 0, 17 }, + Package(){0x0007FFFF, 3, 0, 18 }, + + /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ /* Bus 0, Dev 9 - PCIe Bridge for network card */ Package(){0x0009FFFF, 0, 0, 17 }, - /* Package(){0x0009FFFF, 1, 0, 16 }, */ - /* Package(){0x0009FFFF, 2, 0, 17 }, */ - /* Package(){0x0009FFFF, 3, 0, 18 }, */ + Package(){0x0009FFFF, 1, 0, 18 }, + Package(){0x0009FFFF, 2, 0, 19 }, + Package(){0x0009FFFF, 3, 0, 16 }, + /* Bus 0, Dev A - PCIe Bridge for network card */ Package(){0x000AFFFF, 0, 0, 18 }, - /* Package(){0x000AFFFF, 1, 0, 16 }, */ - /* Package(){0x000AFFFF, 2, 0, 17 }, */ - /* Package(){0x000AFFFF, 3, 0, 18 }, */ - /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ + Package(){0x000AFFFF, 1, 0, 19 }, + Package(){0x000AFFFF, 2, 0, 16 }, + Package(){0x000AFFFF, 3, 0, 17 }, + + /* Bus 0, Dev b - */ + Package(){0x000BFFFF, 0, 0, 19 }, + Package(){0x000BFFFF, 1, 0, 16 }, + Package(){0x000BFFFF, 2, 0, 17 }, + Package(){0x000BFFFF, 3, 0, 18 }, + + /* Bus 0, Dev c - */ + Package(){0x000CFFFF, 0, 0, 16 }, + Package(){0x000CFFFF, 1, 0, 17 }, + Package(){0x000CFFFF, 2, 0, 18 }, + Package(){0x000CFFFF, 3, 0, 19 }, - /* SB devices in APIC mode */ - /* Bus 0, Dev 17 - SATA controller #2 */ - /* Bus 0, Dev 18 - SATA controller #1 */ + /* Bus 0, Dev 17 - SATA controller */ Package(){0x0011FFFF, 0, 0, 22 }, /* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */ Package(){0x0012FFFF, 0, 0, 16 }, Package(){0x0012FFFF, 1, 0, 17 }, + Package(){0x0012FFFF, 2, 0, 18 }, + Package(){0x0012FFFF, 3, 0, 19 }, + Package(){0x0013FFFF, 0, 0, 18 }, Package(){0x0013FFFF, 1, 0, 19 }, - Package(){0x0014FFFF, 0, 0, 16 }, + Package(){0x0013FFFF, 2, 0, 16 }, + Package(){0x0013FFFF, 3, 0, 17 }, /* Package(){0x00130004, 2, 0, 18 }, */ /* Package(){0x00130005, 3, 0, 19 }, */ - /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:AC97 Audio; F6:AC97 Modem */ + /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:AC97 Audio;F6:AC97 Modem */ Package(){0x0014FFFF, 0, 0, 16 }, Package(){0x0014FFFF, 1, 0, 17 }, Package(){0x0014FFFF, 2, 0, 18 }, @@ -214,10 +264,10 @@ Name(APS5, Package(){ /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, + Package(){0x0000FFFF, 0, 0, 45 }, + Package(){0x0000FFFF, 1, 0, 46 }, + Package(){0x0000FFFF, 2, 0, 47 }, + Package(){0x0000FFFF, 3, 0, 44 }, }) Name(PS6, Package(){ @@ -230,10 +280,10 @@ Name(APS6, Package(){ /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, + Package(){0x0000FFFF, 0, 0, 46 }, + Package(){0x0000FFFF, 1, 0, 47 }, + Package(){0x0000FFFF, 2, 0, 44 }, + Package(){0x0000FFFF, 3, 0, 45 }, }) Name(PS7, Package(){ @@ -246,17 +296,18 @@ Name(APS7, Package(){ /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, + Package(){0x0000FFFF, 0, 0, 47 }, + Package(){0x0000FFFF, 1, 0, 44 }, + Package(){0x0000FFFF, 2, 0, 45 }, + Package(){0x0000FFFF, 3, 0, 46 }, }) + Name(PS9, Package(){ /* PCIe slot - Hooked to PCIe slot 9 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, }) Name(APS9, Package(){ @@ -268,10 +319,10 @@ }) Name(PSa, Package(){ /* PCIe slot - Hooked to PCIe slot 10 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, }) Name(APSa, Package(){ @@ -282,6 +333,38 @@ Package(){0x0000FFFF, 3, 0, 17 }, }) + Name(PSb, Package(){ + /* PCIe slot - Hooked to PCIe slot 11 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + + Name(APSb, Package(){ + /* PCIe slot - Hooked to PCIe slot 11 */ + Package(){0x0000FFFF, 0, 0, 32 }, + Package(){0x0000FFFF, 1, 0, 33 }, + Package(){0x0000FFFF, 2, 0, 34 }, + Package(){0x0000FFFF, 3, 0, 34 }, + }) + + Name(PSc, Package(){ + /* PCIe slot - Hooked to PCIe slot 12 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + + Name(APSc, Package(){ + /* PCIe slot - Hooked to PCIe slot 12 */ + Package(){0x0000FFFF, 0, 0, 36 }, + Package(){0x0000FFFF, 1, 0, 37 }, + Package(){0x0000FFFF, 2, 0, 38 }, + Package(){0x0000FFFF, 3, 0, 39 }, + }) + Name(PCIB, Package(){ /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */ Package(){0x0005FFFF, 0, 0, 0x14 }, Modified: trunk/src/mainboard/supermicro/h8scm_fam10/acpi_tables.c ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/acpi_tables.c Tue Mar 22 14:40:09 2011 (r6459) +++ trunk/src/mainboard/supermicro/h8scm_fam10/acpi_tables.c Mon Mar 28 06:38:14 2011 (r6466) @@ -65,12 +65,25 @@ unsigned long acpi_fill_madt(unsigned long current) { + device_t dev; + u32 dword; + u32 gsi_base=0; /* create all subtables for processors */ current = acpi_create_madt_lapics(current); /* Write SB700 IOAPIC, only one */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, - IO_APIC_ADDR, 0); + IO_APIC_ADDR, gsi_base); + /* IOAPIC on rs5690 */ + gsi_base += 24; /* SB700 has 24 IOAPIC entries. */ + dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + if (dev) { + pci_write_config32(dev, 0xF8, 0x1); + dword = pci_read_config32(dev, 0xFC) & 0xfffffff0; + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2+1, + dword, gsi_base); + } + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 0); Modified: trunk/src/mainboard/supermicro/h8scm_fam10/devicetree.cb ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/devicetree.cb Tue Mar 22 14:40:09 2011 (r6459) +++ trunk/src/mainboard/supermicro/h8scm_fam10/devicetree.cb Mon Mar 28 06:38:14 2011 (r6466) @@ -1,39 +1,42 @@ -# sample config for amd/tilapia_fam10 +# GPP1 (dev2,3) --> slot 7 +# GPP2 (dev12) --> slot 6 +# GPP3A (dev9,A) --> Lan1, Lan2 + +# sample config for supermicro/h8scm_fam10 chip northbridge/amd/amdfam10/root_complex device lapic_cluster 0 on - chip cpu/amd/socket_AM3 #L1 and DDR3 + chip cpu/amd/socket_C32 #L1 and DDR3 device lapic 0 on end end end device pci_domain 0 on - subsystemid 0x1022 0x3060 inherit + subsystemid 0x15d9 0x1511 inherit chip northbridge/amd/amdfam10 + ##device pci 18.0 on end + ##device pci 18.0 on end device pci 18.0 on # northbridge - chip southbridge/amd/rs780 + chip southbridge/amd/sr5650 device pci 0.0 on end # HT 0x9600 - device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 + device pci 0.1 on end # CLKCONFIG device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 - device pci 3.0 on end # PCIE P2P bridge 0x960b - device pci 4.0 on end # PCIE P2P bridge 0x9604 + device pci 3.0 off end # PCIE P2P bridge 0x960b + device pci 4.0 off end # PCIE P2P bridge 0x9604 device pci 5.0 off end # PCIE P2P bridge 0x9605 - device pci 6.0 off end # PCIE P2P bridge 0x9606 - device pci 7.0 off end # PCIE P2P bridge 0x9607 - device pci 8.0 off end # NB/SB Link P2P bridge - device pci 9.0 on end # - device pci a.0 on end # - register "gppsb_configuration" = "1" # Configuration B - register "gpp_configuration" = "3" # Configuration D default - register "port_enable" = "0x6fc" - register "gfx_dev2_dev3" = "1" - register "gfx_dual_slot" = "2" - - register "gfx_lane_reversal" = "0" - register "gfx_tmds" = "0" - register "gfx_compliance" = "0" - register "gfx_reconfiguration" = "1" - register "gfx_link_width" = "0" + device pci 6.0 on end # PCIE P2P bridge 0x9606 + device pci 7.0 on end # PCIE P2P bridge 0x9607 + device pci 8.0 on end # NB/SB Link P2P bridge + device pci 9.0 on end # + device pci a.0 on end # + device pci b.0 on end # + device pci c.0 on end # + device pci d.0 on end # + register "gpp1_configuration" = "0" # Configuration 16:0 default + register "gpp2_configuration" = "1" # Configuration 8:8 + #register "gpp3a_configuration" = "2" # Configuration 4:1:1:0:0:0 + register "gpp3a_configuration" = "11" # Configuration 1:1:1:1:1:1 + register "port_enable" = "0x1ffc" end - chip southbridge/amd/sb700 # it is under NB/SB Link, but on the same pri bus + chip southbridge/amd/sp5100 # it is under NB/SB Link, but on the same pri bus device pci 11.0 on end # SATA device pci 12.0 on end # USB device pci 12.1 on end # USB @@ -41,75 +44,65 @@ device pci 13.0 on end # USB device pci 13.1 on end # USB device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - end # SM + device pci 14.0 on end # SM device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 + device pci 14.2 off end # HDA 0x4383, h8scm doesnt have codec. device pci 14.3 on # LPC 0x439d - chip superio/ite/it8718f + chip superio/winbond/w83627hf device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 off end # EC - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 on # Mouse - irq 0x70 = 12 + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 off # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 end - device pnp 2e.7 off # GPIO, must be closed for unresolved reason. - end - device pnp 2e.8 off # MIDI - io 0x60 = 0x300 - irq 0x70 = 9 + device pnp 2e.6 off # SFI + io 0x62 = 0x100 end - device pnp 2e.9 off # GAME + device pnp 2e.7 off # GPIO_GAME_MIDI io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 end - device pnp 2e.a off end # CIR - end #superio/ite/it8718f + device pnp 2e.8 off end # WDTO_PLED + device pnp 2e.9 off end # GPIO_SUSLED + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end #superio/winbond/w83627hf end #LPC device pci 14.4 on end # PCI 0x4384 device pci 14.5 on end # USB 2 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/sb700 + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + end #southbridge/amd/sp5100 end # device pci 18.0 - - device pci 18.0 on end - device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end device pci 18.4 on end -# device pci 00.5 on end + device pci 19.0 on end + device pci 19.1 on end + device pci 19.2 on end + device pci 19.3 on end + device pci 19.4 on end end end #pci_domain #for node 32 to node 63 @@ -140,4 +133,7 @@ # device pnp 0.9 off end # mcp55 # device pnp 0.a on end # GH ext table # end + end + + Modified: trunk/src/mainboard/supermicro/h8scm_fam10/dsdt.asl ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/dsdt.asl Tue Mar 22 14:40:09 2011 (r6459) +++ trunk/src/mainboard/supermicro/h8scm_fam10/dsdt.asl Mon Mar 28 06:38:14 2011 (r6466) @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Advanced Micro Devices, Inc. + * Copyright (C) 2009 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -19,11 +19,11 @@ /* DefinitionBlock Statement */ DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - "AMD ", /* OEMID */ - "TILAPIA ", /* TABLE ID */ + "AMD ", /* OEMID */ + "H8SCM ", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ @@ -98,6 +98,24 @@ ) { #include "acpi/cpstate.asl" } + + Processor( + CPU4, /* name space name */ + 4, /* Unique number for this processor */ + 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + #include "acpi/cpstate.asl" + } + + Processor( + CPU5, /* name space name */ + 5, /* Unique number for this processor */ + 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + #include "acpi/cpstate.asl" + } } /* End _PR scope */ /* PIC IRQ mapping registers, C00h-C01h */ @@ -1160,7 +1178,7 @@ #include "acpi/usb.asl" - /* South Bridge */ + /* System Bus */ Scope(\_SB) { /* Start \_SB scope */ #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ @@ -1266,6 +1284,24 @@ } /* end _PRT */ } /* end PBRa */ + Device(PBRb) { + Name(_ADR, 0x000b0000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APSb) } /* APIC mode */ + Return (PSb) /* PIC Mode */ + } /* end _PRT */ + } /* end PBRb */ + + Device(PBRc) { + Name(_ADR, 0x000c0000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APSc) } /* APIC mode */ + Return (PSc) /* PIC Mode */ + } /* end _PRT */ + } /* end PBRc */ + /* PCI slot 1, 2, 3 */ Device(PIBR) { @@ -1544,6 +1580,7 @@ 0xF300 /* length */ ) +#if 0 Memory32Fixed(READWRITE, 0, 0xA0000, BSMM) Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ @@ -1585,12 +1622,16 @@ ,, PEBM ) +#endif + /* memory space for PCI BARs below 4GB */ + Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) }) /* End Name(_SB.PCI0.CRES) */ Method(_CRS, 0) { /* DBGO("\\_SB\\PCI0\\_CRS\n") */ +#if 0 CreateDWordField(CRES, ^EMM1._BAS, EM1B) CreateDWordField(CRES, ^EMM1._LEN, EM1L) CreateDWordField(CRES, ^DMLO._BAS, DMLB) @@ -1614,8 +1655,7 @@ /* * If(LNotEqual(TOM2, 0x00000000)){ * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * ShiftLeft(TOM2, 20, Local0) - * Subtract(Local0, 0x100000000, DMHL) + * Subtract(TOM2, 0x100000000, DMHL) * } */ @@ -1628,6 +1668,22 @@ ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */ Store(PBLN,EBML) } +#endif + + CreateDWordField(CRES, ^MMIO._BAS, MM1B) + CreateDWordField(CRES, ^MMIO._LEN, MM1L) + /* + * Declare memory between TOM1 and 4GB as available + * for PCI MMIO. + * Use ShiftLeft to avoid 64bit constant (for XP). + * This will work even if the OS does 32bit arithmetic, as + * 32bit (0x00000000 - TOM1) will wrap and give the same + * result as 64bit (0x100000000 - TOM1). + */ + Store(TOM1, MM1B) + ShiftLeft(0x10000000, 4, Local0) + Subtract(Local0, TOM1, Local0) + Store(Local0, MM1L) Return(CRES) /* note to change the Name buffer */ } /* end of Method(_SB.PCI0._CRS) */ Modified: trunk/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/get_bus_conf.c Tue Mar 22 14:40:09 2011 (r6459) +++ trunk/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c Mon Mar 28 06:38:14 2011 (r6466) @@ -32,9 +32,10 @@ /* Global variables for MB layouts and these will be shared by irqtable mptable * and acpi_tables busnum is default. */ -u8 bus_rs780[11]; -u8 bus_sb700[2]; -u32 apicid_sb700; +u8 bus_isa; +u8 bus_sr5650[14]; +u8 bus_sp5100[2]; +u32 apicid_sp5100; /* * Here you only need to set value in pci1234 for HT-IO that could be installed or not @@ -53,8 +54,10 @@ 0x20202020, }; -u32 sbdn_rs780; -u32 sbdn_sb700; +u32 bus_type[256]; + +u32 sbdn_sr5650; +u32 sbdn_sp5100; extern void get_pci1234(void); @@ -64,7 +67,7 @@ { u32 apicid_base; device_t dev; - int i; + int i, j; if (get_bus_conf_done == 1) return; /* do it only once */ @@ -79,38 +82,56 @@ get_pci1234(); sysconf.sbdn = (sysconf.hcdn[0] & 0xff); - sbdn_rs780 = sysconf.sbdn; - sbdn_sb700 = 0; + sbdn_sr5650 = sysconf.sbdn; + sbdn_sp5100 = 0; for (i = 0; i < 2; i++) { - bus_sb700[i] = 0; + bus_sp5100[i] = 0; + } + for (i = 0; i < ARRAY_SIZE(bus_sr5650); i++) { + bus_sr5650[i] = 0; } - for (i = 0; i < ARRAY_SIZE(bus_rs780); i++) { - bus_rs780[i] = 0; + + for (i = 0; i < 256; i++) { + bus_type[i] = 0; /* default ISA bus. */ } - bus_rs780[0] = (sysconf.pci1234[0] >> 16) & 0xff; - bus_sb700[0] = bus_rs780[0]; + bus_type[0] = 1; /* pci */ + + bus_sr5650[0] = (sysconf.pci1234[0] >> 16) & 0xff; + bus_sp5100[0] = bus_sr5650[0]; + + bus_type[bus_sr5650[0]] = 1; - /* sb700 */ - dev = dev_find_slot(bus_sb700[0], PCI_DEVFN(sbdn_sb700 + 0x14, 4)); + /* sp5100 */ + dev = dev_find_slot(bus_sp5100[0], PCI_DEVFN(sbdn_sp5100 + 0x14, 4)); if (dev) { - bus_sb700[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_sp5100[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + for (j = bus_sp5100[1]; j < bus_isa; j++) + bus_type[j] = 1; } - /* rs780 */ - for (i = 1; i < ARRAY_SIZE(bus_rs780); i++) { - dev = dev_find_slot(bus_rs780[0], PCI_DEVFN(sbdn_rs780 + i, 0)); + /* sr5650 */ + for (i = 1; i < ARRAY_SIZE(bus_sr5650); i++) { + dev = dev_find_slot(bus_sr5650[0], PCI_DEVFN(sbdn_sr5650 + i, 0)); if (dev) { - bus_rs780[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_sr5650[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); + if(255 != bus_sr5650[i]) { + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + bus_type[bus_sr5650[i]] = 1; /* PCI bus. */ + } } } /* I/O APICs: APIC ID Version State Address */ + bus_isa = 10; #if CONFIG_LOGICAL_CPUS==1 apicid_base = get_apicid_base(1); #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif - apicid_sb700 = apicid_base + 0; + apicid_sp5100 = apicid_base + 0; } Modified: trunk/src/mainboard/supermicro/h8scm_fam10/irq_tables.c ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/irq_tables.c Tue Mar 22 14:40:09 2011 (r6459) +++ trunk/src/mainboard/supermicro/h8scm_fam10/irq_tables.c Mon Mar 28 06:38:14 2011 (r6466) @@ -45,9 +45,10 @@ pirq_info->slot = slot; pirq_info->rfu = rfu; } +extern u8 bus_isa; extern u8 bus_rs780[8]; -extern u8 bus_sb700[2]; -extern unsigned long sbdn_sb700; +extern u8 bus_sp5100[2]; +extern unsigned long sbdn_sp5100; unsigned long write_pirq_routing_table(unsigned long addr) { @@ -74,8 +75,8 @@ pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - pirq->rtr_bus = bus_sb700[0]; - pirq->rtr_devfn = ((sbdn_sb700 + 0x14) << 3) | 4; + pirq->rtr_bus = bus_sp5100[0]; + pirq->rtr_devfn = ((sbdn_sp5100 + 0x14) << 3) | 4; pirq->exclusive_irqs = 0; @@ -90,7 +91,7 @@ slot_num = 0; /* pci bridge */ - write_pirq_info(pirq_info, bus_sb700[0], ((sbdn_sb700 + 0x14) << 3) | 4, + write_pirq_info(pirq_info, bus_sp5100[0], ((sbdn_sp5100 + 0x14) << 3) | 4, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; Modified: trunk/src/mainboard/supermicro/h8scm_fam10/mainboard.c ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/mainboard.c Tue Mar 22 14:40:09 2011 (r6459) +++ trunk/src/mainboard/supermicro/h8scm_fam10/mainboard.c Mon Mar 28 06:38:14 2011 (r6466) @@ -26,281 +26,78 @@ #include <cpu/amd/mtrr.h> #include <device/pci_def.h> #include <southbridge/amd/sb700/sb700.h> +#include <southbridge/amd/sr5650/cmn.h> #include "chip.h" -#define ADT7461_ADDRESS 0x4C -#define ARA_ADDRESS 0x0C /* Alert Response Address */ - -extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); -extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, - u8 val); - -#define ADT7461_read_byte(address) \ - do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address) -#define ARA_read_byte(address) \ - do_smbus_read_byte(SMBUS_IO_BASE, ARA_ADDRESS, address) -#define ADT7461_write_byte(address, val) \ - do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val) - #define SMBUS_IO_BASE 0x6000 uint64_t uma_memory_base, uma_memory_size; -void set_pcie_dereset(void); void set_pcie_reset(void); +void set_pcie_dereset(void); u8 is_dev3_present(void); -void set_pcie_dereset() -{ - u8 byte; - u16 word; - device_t sm_dev; - /* set 0 to bit1 :disable GPM9 as SLP_S2 output */ - /* set 0 to bit2 :disable GPM8 as AZ_RST output */ - byte = pm_ioread(0x8d); - byte &= ~((1 << 1) | (1 << 2)); - pm_iowrite(0x8d, byte); - - /* set the GPM8 and GPM9 output enable and the value to 1 */ - byte = pm_ioread(0x94); - byte &= ~((1 << 2) | (1 << 3)); - byte |= ((1 << 0) | (1 << 1)); - pm_iowrite(0x94, byte); - - /* set the GPIO65 output enable and the value is 1 */ - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); - word = pci_read_config16(sm_dev, 0x7e); - word |= (1 << 0); - word &= ~(1 << 4); - pci_write_config16(sm_dev, 0x7e, word); -} - -void set_pcie_reset() -{ - u8 byte; - u16 word; - device_t sm_dev; - - /* set 0 to bit1 :disable GPM9 as SLP_S2 output */ - /* set 0 to bit2 :disable GPM8 as AZ_RST output */ - byte = pm_ioread(0x8d); - byte &= ~((1 << 1) | (1 << 2)); - pm_iowrite(0x8d, byte); - - /* set the GPM8 and GPM9 output enable and the value to 0 */ - byte = pm_ioread(0x94); - byte &= ~((1 << 2) | (1 << 3)); - byte &= ~((1 << 0) | (1 << 1)); - pm_iowrite(0x94, byte); - - /* set the GPIO65 output enable and the value is 0 */ - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); - word = pci_read_config16(sm_dev, 0x7e); - word &= ~(1 << 0); - word &= ~(1 << 4); - pci_write_config16(sm_dev, 0x7e, word); -} - -#if 0 /* TODO: */ -/******************************************************** -* tilapia uses SB700 GPIO8 to detect IDE_DMA66. -* IDE_DMA66 is routed to GPIO 8. So we read Gpio 8 to -* get the cable type, 40 pin or 80 pin? -********************************************************/ -static void get_ide_dma66(void) -{ - u8 byte; - /*u32 sm_dev, ide_dev; */ - device_t sm_dev, ide_dev; - - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); - - byte = pci_read_config8(sm_dev, 0xA9); - byte |= (1 << 4); /* Set Gpio8 as input */ - pci_write_config8(sm_dev, 0xA9, byte); - - ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1)); - byte = pci_read_config8(ide_dev, 0x56); - byte &= ~(7 << 0); - if ((1 << 4) & pci_read_config8(sm_dev, 0xAA)) - byte |= 2 << 0; /* mode 2 */ - else - byte |= 5 << 0; /* mode 5 */ - pci_write_config8(ide_dev, 0x56, byte); -} -#endif - -/* - * justify the dev3 is exist or not - */ +/* 780 board use this function*/ u8 is_dev3_present(void) { - u16 word; - device_t sm_dev; - - /* access the smbus extended register */ - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); - - /* put the GPIO68 output to tristate */ - word = pci_read_config16(sm_dev, 0x7e); - word |= 1 << 6; - pci_write_config16(sm_dev, 0x7e,word); - - /* read the GPIO68 input status */ - word = pci_read_config16(sm_dev, 0x7e); - - if(word & (1 << 10)){ - /*not exist*/ - return 0; - }else{ - /*exist*/ - return 1; - } -} - - -/* - * set gpio40 gfx - */ -static void set_gpio40_gfx(void) -{ - u8 byte; - u32 dword; - device_t sm_dev; - /* disable the GPIO40 as CLKREQ2# function */ - byte = pm_ioread(0xd3); - byte &= ~(1 << 7); - pm_iowrite(0xd3, byte); - - /* disable the GPIO40 as CLKREQ3# function */ - byte = pm_ioread(0xd4); - byte &= ~(1 << 0); - pm_iowrite(0xd4, byte); - - /* enable pull up for GPIO68 */ - byte = pm2_ioread(0xf1); - byte &= ~(1 << 4); - pm2_iowrite(0xf1, byte); - - /* access the smbus extended register */ - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); - - /*if the dev3 is present, set the gfx to 2x8 lanes*/ - /*otherwise set the gfx to 1x16 lanes*/ - if(is_dev3_present()){ - - printk(BIOS_INFO, "Dev3 is present. GFX Configuration is Two x8 slots\n"); - /* when the gpio40 is configured as GPIO, this will enable the output */ - pci_write_config32(sm_dev, 0xf8, 0x4); - dword = pci_read_config32(sm_dev, 0xfc); - dword &= ~(1 << 10); - - /* When the gpio40 is configured as GPIO, this will represent the output value*/ - /* 1 :enable two x8 , 0 : master slot enable only */ - dword |= (1 << 26); - pci_write_config32(sm_dev, 0xfc, dword); - - }else{ - printk(BIOS_INFO, "Dev3 is not present. GFX Configuration is One x16 slot\n"); - /* when the gpio40 is configured as GPIO, this will enable the output */ - pci_write_config32(sm_dev, 0xf8, 0x4); - dword = pci_read_config32(sm_dev, 0xfc); - dword &= ~(1 << 10); - - /* When the gpio40 is configured as GPIO, this will represent the output value*/ - /* 1 :enable two x8 , 0 : master slot enable only */ - dword &= ~(1 << 26); - pci_write_config32(sm_dev, 0xfc, dword); - } + return 0; } /* - * set thermal config - */ -static void set_thermal_config(void) -{ - u8 byte; - u16 word; - device_t sm_dev; - - /* set ADT 7461 */ - ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */ - ADT7461_write_byte(0x0C, 0x00); /* Local Temperature Low limit */ - ADT7461_write_byte(0x0D, 0x50); /* External Temperature Hight limit High Byte */ - ADT7461_write_byte(0x0E, 0x00); /* External Temperature Low limit High Byte */ - - ADT7461_write_byte(0x19, 0x55); /* External THERM limit */ - ADT7461_write_byte(0x20, 0x55); /* Local THERM limit */ - - byte = ADT7461_read_byte(0x02); /* read status register to clear it */ - ARA_read_byte(0x05); /* A hardware alert can only be cleared by the master sending an ARA as a read command */ - printk(BIOS_INFO, "Init adt7461 end , status 0x02 %02x\n", byte); - - /* sb700 settings for thermal config */ - /* set SB700 GPIO 64 to GPIO with pull-up */ - byte = pm2_ioread(0x42); - byte &= 0x3f; - pm2_iowrite(0x42, byte); - - /* set GPIO 64 to input */ - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); - word = pci_read_config16(sm_dev, 0x56); - word |= 1 << 7; - pci_write_config16(sm_dev, 0x56, word); - - /* set GPIO 64 internal pull-up */ - byte = pm2_ioread(0xf0); - byte &= 0xee; - pm2_iowrite(0xf0, byte); - - /* set Talert to be active low */ - byte = pm_ioread(0x67); - byte &= ~(1 << 5); - pm_iowrite(0x67, byte); - - /* set Talert to generate ACPI event */ - byte = pm_ioread(0x3c); - byte &= 0xf3; - pm_iowrite(0x3c, byte); - - /* THERMTRIP pin */ - /* byte = pm_ioread(0x68); - * byte |= 1 << 3; - * pm_iowrite(0x68, byte); - * - * byte = pm_ioread(0x55); - * byte |= 1 << 0; - * pm_iowrite(0x55, byte); - * - * byte = pm_ioread(0x67); - * byte &= ~( 1 << 6); - * pm_iowrite(0x67, byte); - */ + * TODO: Add the routine info of each PCIE_RESET_L. + * TODO: Add the reset of each PCIE_RESET_L. + * PCIE_RESET_GPIO1 -> Slot 0 + * PCIE_RESET_GPIO2 -> On-board NIC Bcm5709 + * PCIE_RESET_GPIO3 -> TMS + * PCIE_RESET_GPIO4 -> Slot 1 + * PCIE_RESET_GPIO5 -> Slot 2 + ***/ +void set_pcie_reset(void) +{ + device_t pcie_core_dev; + + pcie_core_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + set_htiu_enable_bits(pcie_core_dev, 0xA8, 0xFFFFFFFF, 0x28282828); + set_htiu_enable_bits(pcie_core_dev, 0xA9, 0x000000FF, 0x00000028); +} + +void set_pcie_dereset(void) +{ + device_t pcie_core_dev; + + pcie_core_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + set_htiu_enable_bits(pcie_core_dev, 0xA8, 0xFFFFFFFF, 0x6F6F6F6F); + set_htiu_enable_bits(pcie_core_dev, 0xA9, 0x000000FF, 0x0000006F); } /************************************************* -* enable the dedicated function in tilapia board. -* This function called early than rs780_enable. +* enable the dedicated function in h8scm board. +* This function called early than sr5650_enable. *************************************************/ -static void tilapia_enable(device_t dev) +static void h8scm_enable(device_t dev) { - printk(BIOS_INFO, "Mainboard TILAPIA Enable. dev=0x%p\n", dev); + /* Leave it for furture use. */ + /* struct mainboard_config *mainboard = + (struct mainboard_config *)dev->chip_info; */ + + printk(BIOS_INFO, "Mainboard H8SCM Enable. dev=0x%p\n", dev); -#if (CONFIG_GFXUMA == 1) msr_t msr, msr2; /* TOP_MEM: the top of DRAM below 4G */ msr = rdmsr(TOP_MEM); - printk(BIOS_INFO, - "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", + printk + (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", __func__, msr.lo, msr.hi); /* TOP_MEM2: the top of DRAM above 4G */ msr2 = rdmsr(TOP_MEM2); - printk(BIOS_INFO, - "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n", + printk + (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n", __func__, msr2.lo, msr2.hi); +#if (CONFIG_GFXUMA == 1) + /* refer to UMA Size Consideration in 780 BDG. */ switch (msr.lo) { case 0x10000000: /* 256M system memory */ uma_memory_size = 0x4000000; /* 64M recommended UMA */ @@ -314,21 +111,16 @@ uma_memory_size = 0x10000000; /* 256M recommended UMA */ break; } - +#else + /* TODO: TOP_MEM2 */ + uma_memory_size = 0;//0x8000000; /* 128M recommended UMA */ +#endif uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", __func__, uma_memory_size, uma_memory_base); - /* TODO: TOP_MEM2 */ -#else - uma_memory_size = 0x8000000; /* 128M recommended UMA */ - uma_memory_base = 0x38000000; /* 1GB system memory supposed */ -#endif - set_pcie_dereset(); /* get_ide_dma66(); */ - set_thermal_config(); - set_gpio40_gfx(); } int add_mainboard_resources(struct lb_memory *mem) @@ -346,6 +138,6 @@ } struct chip_operations mainboard_ops = { - CHIP_NAME("AMD TILAPIA Mainboard") - .enable_dev = tilapia_enable, + CHIP_NAME("AMD H8SCM Mainboard") + .enable_dev = h8scm_enable, }; Modified: trunk/src/mainboard/supermicro/h8scm_fam10/mptable.c ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/mptable.c Tue Mar 22 14:40:09 2011 (r6459) +++ trunk/src/mainboard/supermicro/h8scm_fam10/mptable.c Mon Mar 28 06:38:14 2011 (r6466) @@ -17,6 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ + #include <console/console.h> #include <arch/smp/mpspec.h> #include <device/pci.h> @@ -25,18 +26,20 @@ #include <stdint.h> #include <cpu/amd/amdfam10_sysconf.h> -extern u8 bus_rs780[11]; -extern u8 bus_sb700[2]; +extern u8 bus_sr5650[14]; +extern u8 bus_sp5100[2]; + +extern u32 apicid_sp5100; -extern u32 apicid_sb700; +extern u32 sbdn_sr5650; +extern u32 sbdn_sp5100; -extern u32 sbdn_rs780; -extern u32 sbdn_sb700; static void *smp_write_config_table(void *v) { struct mp_config_table *mc; int bus_isa; + u32 apicid_sr5650; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); @@ -46,20 +49,21 @@ get_bus_conf(); - mptable_write_buses(mc, NULL, &bus_isa); + apicid_sp5100 = 0x20; + apicid_sr5650 = apicid_sp5100 + 1; + mptable_write_buses(mc, NULL, &bus_isa); /* I/O APICs: APIC ID Version State Address */ { device_t dev; u32 dword; u8 byte; - dev = - dev_find_slot(bus_sb700[0], - PCI_DEVFN(sbdn_sb700 + 0x14, 0)); + dev = dev_find_slot(0, //bus_sp5100[0], TODO: why bus_sp5100[0] use same value of bus_sr5650[0] assigned by get_pci1234(), instead of 0. + PCI_DEVFN(sbdn_sp5100 + 0x14, 0)); if (dev) { dword = pci_read_config32(dev, 0x74) & 0xfffffff0; - smp_write_ioapic(mc, apicid_sb700, 0x11, dword); + smp_write_ioapic(mc, apicid_sp5100, 0x11, dword); /* Initialize interrupt mapping */ /* aza */ @@ -89,70 +93,80 @@ * 00:14.6: INTB MCI */ } + dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + if (dev) { + pci_write_config32(dev, 0xF8, 0x1); + dword = pci_read_config32(dev, 0xFC) & 0xfffffff0; + smp_write_ioapic(mc, apicid_sp5100+1, 0x11, dword); + } } /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0); + mptable_add_isa_interrupts(mc, bus_isa, apicid_sp5100, 0); /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ #if CONFIG_GENERATE_ACPI_TABLES == 0 #define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin)) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sp5100, (pin)) #else #define PCI_INT(bus, dev, fn, pin) #endif - /* usb */ PCI_INT(0x0, 0x12, 0x0, 0x10); /* USB */ PCI_INT(0x0, 0x12, 0x1, 0x11); PCI_INT(0x0, 0x13, 0x0, 0x12); PCI_INT(0x0, 0x13, 0x1, 0x13); - PCI_INT(0x0, 0x14, 0x0, 0x10); + //PCI_INT(0x0, 0x14, 0x0, 0x10); /* sata */ PCI_INT(0x0, 0x11, 0x0, 0x16); /* HD Audio: b0:d20:f1:reg63 should be 0. */ - /* PCI_INT(0x0, 0x14, 0x2, 0x12); */ + PCI_INT(0x0, 0x14, 0x2, 0x10); /* on board NIC & Slot PCIE. */ - /* PCI_INT(bus_rs780[0x1], 0x5, 0x0, 0x12); */ -/* PCI_INT(bus_rs780[0x1], 0x5, 0x1, 0x13); */ - PCI_INT(bus_rs780[0x2], 0x0, 0x0, 0x12); /* Dev 2, external GFX */ - /* PCI_INT(bus_rs780[0x3], 0x0, 0x0, 0x13); */ - PCI_INT(bus_rs780[0x4], 0x0, 0x0, 0x10); /* configuration B doesnt need dev 5,6,7 */ /* - * PCI_INT(bus_rs780[0x5], 0x0, 0x0, 0x11); - * PCI_INT(bus_rs780[0x6], 0x0, 0x0, 0x12); - * PCI_INT(bus_rs780[0x7], 0x0, 0x0, 0x13); + * PCI_INT(bus_sr5650[0x5], 0x0, 0x0, 0x11); + * PCI_INT(bus_sr5650[0x6], 0x0, 0x0, 0x12); + * PCI_INT(bus_sr5650[0x7], 0x0, 0x0, 0x13); */ - PCI_INT(bus_rs780[0x9], 0x0, 0x0, 0x11); - PCI_INT(bus_rs780[0xA], 0x0, 0x0, 0x12); /* NIC */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((2)<<2)|(0)), apicid_sp5100+1, 28); /* dev 2 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((4)<<2)|(0)), apicid_sp5100+1, 28); /* dev 4 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((12)<<2)|(0)), apicid_sp5100+1, 30); /* dev 11 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((12)<<2)|(0)), apicid_sp5100+1, 30); /* dev 12 */ + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[2], (((0)<<2)|(0)), apicid_sp5100+1, 0); /* card behind dev2 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[4], (((0)<<2)|(0)), apicid_sp5100+1, 20); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[4], (((0)<<2)|(1)), apicid_sp5100+1, 21); /* NIC */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[11], (((0)<<2)|(0)), apicid_sp5100+1, 8); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[11], (((0)<<2)|(1)), apicid_sp5100+1, 9); /* card behind dev11 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[12], (((0)<<2)|(0)), apicid_sp5100+1, 12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[12], (((0)<<2)|(1)), apicid_sp5100+1, 13); /* card behind dev12 */ /* PCI slots */ /* PCI_SLOT 0. */ - PCI_INT(bus_sb700[1], 0x5, 0x0, 0x14); - PCI_INT(bus_sb700[1], 0x5, 0x1, 0x15); - PCI_INT(bus_sb700[1], 0x5, 0x2, 0x16); - PCI_INT(bus_sb700[1], 0x5, 0x3, 0x17); + PCI_INT(bus_sp5100[1], 0x5, 0x0, 0x14); + PCI_INT(bus_sp5100[1], 0x5, 0x1, 0x15); + PCI_INT(bus_sp5100[1], 0x5, 0x2, 0x16); + PCI_INT(bus_sp5100[1], 0x5, 0x3, 0x17); /* PCI_SLOT 1. */ - PCI_INT(bus_sb700[1], 0x6, 0x0, 0x15); - PCI_INT(bus_sb700[1], 0x6, 0x1, 0x16); - PCI_INT(bus_sb700[1], 0x6, 0x2, 0x17); - PCI_INT(bus_sb700[1], 0x6, 0x3, 0x14); + PCI_INT(bus_sp5100[1], 0x6, 0x0, 0x15); + PCI_INT(bus_sp5100[1], 0x6, 0x1, 0x16); + PCI_INT(bus_sp5100[1], 0x6, 0x2, 0x17); + PCI_INT(bus_sp5100[1], 0x6, 0x3, 0x14); /* PCI_SLOT 2. */ - PCI_INT(bus_sb700[1], 0x7, 0x0, 0x16); - PCI_INT(bus_sb700[1], 0x7, 0x1, 0x17); - PCI_INT(bus_sb700[1], 0x7, 0x2, 0x14); - PCI_INT(bus_sb700[1], 0x7, 0x3, 0x15); + PCI_INT(bus_sp5100[1], 0x7, 0x0, 0x16); + PCI_INT(bus_sp5100[1], 0x7, 0x1, 0x17); + PCI_INT(bus_sp5100[1], 0x7, 0x2, 0x14); + PCI_INT(bus_sp5100[1], 0x7, 0x3, 0x15); /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); Modified: trunk/src/mainboard/supermicro/h8scm_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/romstage.c Tue Mar 22 14:40:09 2011 (r6459) +++ trunk/src/mainboard/supermicro/h8scm_fam10/romstage.c Mon Mar 28 06:38:14 2011 (r6466) @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -//#define SYSTEM_TYPE 0 /* SERVER */ +//#define SYSTEM_TYPE 0 /* SERVER */ //FIXME SERVER enable ECC, cause linux hang #define SYSTEM_TYPE 1 /* DESKTOP */ //#define SYSTEM_TYPE 2 /* MOBILE */ @@ -42,16 +42,18 @@ #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> #include "cpu/x86/bist.h" -#include "superio/ite/it8718f/early_serial.c" +#include "superio/nuvoton/wpcm450/early_init.c" #include <usbdebug.h> #include "cpu/x86/mtrr/earlymtrr.c" #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" -#include "southbridge/amd/rs780/early_setup.c" #include "southbridge/amd/sb700/early_setup.c" +#include "southbridge/amd/sr5650/early_setup.c" #include "northbridge/amd/amdfam10/debug.c" -static void activate_spd_rom(const struct mem_controller *ctrl) { } +static void activate_spd_rom(const struct mem_controller *ctrl) +{ +} static int spd_read_byte(u32 device, u32 address) { @@ -69,16 +71,28 @@ #if CONFIG_UPDATE_CPU_MICROCODE #include "cpu/amd/model_10xxx/update_microcode.c" #endif - #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" #include <spd.h> +//#include "spd_addr.h" + +#define RC00 0 + +#define DIMM0 0x50 +#define DIMM1 0x51 +#define DIMM2 0x52 +#define DIMM3 0x53 + void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); - static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; - u32 bsp_apicid = 0, val; + static const u8 spd_addr[] = { + RC00, 0x52, 0x53, 0, 0, 0x50, 0x51, 0, 0, + //RC00, DIMM2, DIMM3, 0, 0, DIMM0, DIMM1, 0, 0, + }; + u32 bsp_apicid = 0; + u32 val; msr_t msr; if (!cpu_init_detectedx && boot_cpu()) { @@ -87,7 +101,9 @@ /* mov bsp to bus 0xff when > 8 nodes */ set_bsp_node_CHtExtNodeCfgEn(); enumerate_ht_chain(); - sb700_pci_port80(); + + disable_pcie_bridge(); + sb7xx_51xx_lpc_port80(); } post_code(0x30); @@ -99,17 +115,20 @@ post_code(0x32); - enable_rs780_dev8(); - sb700_lpc_init(); + enable_sr5650_dev8(); + sb7xx_51xx_lpc_init(); + + sb7xx_51xx_enable_wideio(0, 0x1600); + + wpcm450_enable_dev(WPCM450_SP1, 0x164E, CONFIG_TTYS0_BASE); - it8718f_enable_serial(0, CONFIG_TTYS0_BASE); + sb7xx_51xx_disable_wideio(0); uart_init(); #if CONFIG_USBDEBUG - sb700_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); + sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); early_usbdebug_init(); #endif - console_init(); printk(BIOS_DEBUG, "\n"); @@ -136,6 +155,8 @@ cpuSetAMDMSR(); post_code(0x34); + /* TODO: The Kernel must support 12 processor, otherwise the interrupt + * can not work correctly. */ amd_ht_init(sysinfo); post_code(0x35); @@ -165,8 +186,9 @@ post_code(0x38); /* run _early_setup before soft-reset. */ - rs780_early_setup(); - sb700_early_setup(); + sr5650_early_setup(); + disable_pcie_bridge(); + sb7xx_51xx_early_setup(); #if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); @@ -191,7 +213,7 @@ printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); #endif - rs780_htinit(); + sr5650_htinit(); /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ if (!warm_reset_detect(0)) { @@ -208,7 +230,6 @@ post_code(0x40); -// die("Die Before MCT init."); printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); @@ -221,13 +242,15 @@ dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200); */ +// ram_check(0x00200000, 0x00200000 + (640 * 1024)); +// ram_check(0x40200000, 0x40200000 + (640 * 1024)); + // die("After MCT init before CAR disabled."); - rs780_before_pci_init(); - sb700_before_pci_init(); + sr5650_before_pci_init(); + sb7xx_51xx_before_pci_init(); post_code(0x42); - printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n"); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. } -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
