Author: svens
Date: Wed Apr 20 10:57:53 2011
New Revision: 6524
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6524
Log:
pci1x2x: use devicetree register configuration
Signed-off-by: Sven Schnelle <sv...@stackframe.org>
Acked-by: Stefan Reinauer <stefan.reina...@coreboot.org>
Added:
trunk/src/southbridge/ti/pci1x2x/chip.h
Modified:
trunk/src/mainboard/nokia/ip530/Kconfig
trunk/src/mainboard/nokia/ip530/devicetree.cb
trunk/src/southbridge/ti/pci1x2x/pci1x2x.c
Modified: trunk/src/mainboard/nokia/ip530/Kconfig
==============================================================================
--- trunk/src/mainboard/nokia/ip530/Kconfig Wed Apr 20 03:08:25 2011
(r6523)
+++ trunk/src/mainboard/nokia/ip530/Kconfig Wed Apr 20 10:57:53 2011
(r6524)
@@ -45,29 +45,4 @@
int
default 22
-## Configuration for the PCMCIA-Cardbus controller.
-config TI_PCMCIA_CARDBUS_CMDR
- hex
- default 0x0107
-
-config TI_PCMCIA_CARDBUS_CLSR
- hex
- default 0x00
-
-config TI_PCMCIA_CARDBUS_CLTR
- hex
- default 0x40
-
-config TI_PCMCIA_CARDBUS_BCR
- hex
- default 0x07C0
-
-config TI_PCMCIA_CARDBUS_SCR
- hex
- default 0x08449060
-
-config TI_PCMCIA_CARDBUS_MRR
- hex
- default 0x00007522
-
endif # BOARD_NOKIA_IP530
Modified: trunk/src/mainboard/nokia/ip530/devicetree.cb
==============================================================================
--- trunk/src/mainboard/nokia/ip530/devicetree.cb Wed Apr 20 03:08:25
2011 (r6523)
+++ trunk/src/mainboard/nokia/ip530/devicetree.cb Wed Apr 20 10:57:53
2011 (r6524)
@@ -28,6 +28,17 @@
device pci 0.0 on end # Host bridge
device pci 1.0 on end # PCI/AGP bridge
chip southbridge/intel/i82371eb # Southbridge
+ device pci f.0 on
+ chip southbridge/ti/pci1x2x
+ device pci 00.0 on
+
+ end
+ register "cltr" = "0x40"
+ register "bcr" = "0x7c0"
+ register "scr" = "0x08449060"
+ register "mrr" = "0x00007522"
+ end
+ end
device pci 7.0 on # ISA bridge
chip superio/smsc/smscsuperio # Super I/O (SMSC FDC37B787)
device pnp 3f0.0 off end # Floppy (No connector)
Added: trunk/src/southbridge/ti/pci1x2x/chip.h
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ trunk/src/southbridge/ti/pci1x2x/chip.h Wed Apr 20 10:57:53 2011
(r6524)
@@ -0,0 +1,13 @@
+#ifndef SOUTHBRIDGE_TI_PCI1X2X_H
+#define SOUTHBRIDGE_TI_PCI1X2X_H
+
+extern struct chip_operations southbridge_ti_pci1x2x_ops;
+
+struct southbridge_ti_pci1x2x_config {
+ int scr;
+ int mrr;
+ int clsr;
+ int cltr;
+ int bcr;
+};
+#endif
Modified: trunk/src/southbridge/ti/pci1x2x/pci1x2x.c
==============================================================================
--- trunk/src/southbridge/ti/pci1x2x/pci1x2x.c Wed Apr 20 03:08:25 2011
(r6523)
+++ trunk/src/southbridge/ti/pci1x2x/pci1x2x.c Wed Apr 20 10:57:53 2011
(r6524)
@@ -23,44 +23,41 @@
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <console/console.h>
-
-#if (!defined(CONFIG_TI_PCMCIA_CARDBUS_CMDR) || \
- !defined(CONFIG_TI_PCMCIA_CARDBUS_CLSR) || \
- !defined(CONFIG_TI_PCMCIA_CARDBUS_CLTR) || \
- !defined(CONFIG_TI_PCMCIA_CARDBUS_BCR) || \
- !defined(CONFIG_TI_PCMCIA_CARDBUS_SCR) || \
- !defined(CONFIG_TI_PCMCIA_CARDBUS_MRR))
-#error "you must supply these values in your mainboard-specific Kconfig file"
-#endif
+#include "chip.h"
static void ti_pci1x2y_init(struct device *dev)
{
+
printk(BIOS_INFO, "Init of Texas Instruments PCI1x2x PCMCIA/CardBus
controller\n");
+ struct southbridge_ti_pci1x2x_config *conf = dev->chip_info;
- /* Command (offset 04) */
- pci_write_config16(dev, 0x04, CONFIG_TI_PCMCIA_CARDBUS_CMDR);
- /* Cache Line Size (offset 0x0C) */
- pci_write_config8(dev, 0x0C, CONFIG_TI_PCMCIA_CARDBUS_CLSR);
- /* CardBus latency timer (offset 0x1B) */
- pci_write_config8(dev, 0x1B, CONFIG_TI_PCMCIA_CARDBUS_CLTR);
- /* Bridge control (offset 0x3E) */
- pci_write_config16(dev, 0x3E, CONFIG_TI_PCMCIA_CARDBUS_BCR);
+ if (conf) {
+ /* Cache Line Size (offset 0x0C) */
+ pci_write_config8(dev, 0x0C, conf->clsr);
+ /* CardBus latency timer (offset 0x1B) */
+ pci_write_config8(dev, 0x1B, conf->cltr);
+ /* Bridge control (offset 0x3E) */
+ pci_write_config16(dev, 0x3E, conf->bcr);
+ }
/*
* Enable change sub-vendor ID. Clear the bit 5 to enable to write
* to the sub-vendor/device ids at 40 and 42.
*/
pci_write_config32(dev, 0x80, 0x10);
pci_write_config32(dev, 0x40, PCI_VENDOR_ID_NOKIA);
- /* Now write the correct value for SCR. */
- /* System control (offset 0x80) */
- pci_write_config32(dev, 0x80, CONFIG_TI_PCMCIA_CARDBUS_SCR);
- /* Multifunction routing */
- pci_write_config32(dev, 0x8C, CONFIG_TI_PCMCIA_CARDBUS_MRR);
+
+ if (conf) {
+ /* Now write the correct value for SCR. */
+ /* System control (offset 0x80) */
+ pci_write_config32(dev, 0x80, conf->scr);
+ /* Multifunction routing */
+ pci_write_config32(dev, 0x8C, conf->mrr);
+ }
/* Set the device control register (0x92) accordingly. */
pci_write_config8(dev, 0x92, pci_read_config8(dev, 0x92) | 0x02);
}
-static struct device_operations ti_pci1x2y_ops = {
+struct device_operations southbridge_ti_pci1x2x_pciops = {
.read_resources = NULL, //pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
@@ -69,19 +66,23 @@
};
static const struct pci_driver ti_pci1225_driver __pci_driver = {
- .ops = &ti_pci1x2y_ops,
+ .ops = &southbridge_ti_pci1x2x_pciops,
.vendor = PCI_VENDOR_ID_TI,
.device = PCI_DEVICE_ID_TI_1225,
};
static const struct pci_driver ti_pci1420_driver __pci_driver = {
- .ops = &ti_pci1x2y_ops,
+ .ops = &southbridge_ti_pci1x2x_pciops,
.vendor = PCI_VENDOR_ID_TI,
.device = PCI_DEVICE_ID_TI_1420,
};
static const struct pci_driver ti_pci1520_driver __pci_driver = {
- .ops = &ti_pci1x2y_ops,
+ .ops = &southbridge_ti_pci1x2x_pciops,
.vendor = PCI_VENDOR_ID_TI,
.device = PCI_DEVICE_ID_TI_1520,
};
+
+struct chip_operations southbridge_ti_pci1x2x_ops = {
+ CHIP_NAME("TI PCI1x2x Cardbus controller")
+};
--
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