Author: svens Date: Wed Apr 20 10:58:38 2011 New Revision: 6528 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6528
Log: pci1x2x: remove latency/bridge control/cacheline size settings Those settings should be handled by the generic PCI/Cardbus code, and not by the driver itself. Signed-off-by: Sven Schnelle <[email protected]> Acked-by: Sven Schnelle <[email protected]> Modified: trunk/src/mainboard/nokia/ip530/devicetree.cb trunk/src/southbridge/ti/pci1x2x/chip.h trunk/src/southbridge/ti/pci1x2x/pci1x2x.c Modified: trunk/src/mainboard/nokia/ip530/devicetree.cb ============================================================================== --- trunk/src/mainboard/nokia/ip530/devicetree.cb Wed Apr 20 10:58:30 2011 (r6527) +++ trunk/src/mainboard/nokia/ip530/devicetree.cb Wed Apr 20 10:58:38 2011 (r6528) @@ -33,8 +33,6 @@ device pci 00.0 on subsystemid 0x13b8 0x0000 end - register "cltr" = "0x40" - register "bcr" = "0x7c0" register "scr" = "0x08449060" register "mrr" = "0x00007522" end Modified: trunk/src/southbridge/ti/pci1x2x/chip.h ============================================================================== --- trunk/src/southbridge/ti/pci1x2x/chip.h Wed Apr 20 10:58:30 2011 (r6527) +++ trunk/src/southbridge/ti/pci1x2x/chip.h Wed Apr 20 10:58:38 2011 (r6528) @@ -6,8 +6,5 @@ struct southbridge_ti_pci1x2x_config { int scr; int mrr; - int clsr; - int cltr; - int bcr; }; #endif Modified: trunk/src/southbridge/ti/pci1x2x/pci1x2x.c ============================================================================== --- trunk/src/southbridge/ti/pci1x2x/pci1x2x.c Wed Apr 20 10:58:30 2011 (r6527) +++ trunk/src/southbridge/ti/pci1x2x/pci1x2x.c Wed Apr 20 10:58:38 2011 (r6528) @@ -34,12 +34,6 @@ struct southbridge_ti_pci1x2x_config *conf = dev->chip_info; if (conf) { - /* Cache Line Size (offset 0x0C) */ - pci_write_config8(dev, 0x0C, conf->clsr); - /* CardBus latency timer (offset 0x1B) */ - pci_write_config8(dev, 0x1B, conf->cltr); - /* Bridge control (offset 0x3E) */ - pci_write_config16(dev, 0x3E, conf->bcr); /* System control (offset 0x80) */ pci_write_config32(dev, 0x80, conf->scr); /* Multifunction routing */ -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
