Author: stepan Date: Thu Apr 21 22:24:43 2011 New Revision: 6535 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6535
Log: some ifdef --> if fixes Signed-off-by: Stefan Reinauer <[email protected]> Acked-by: Stefan Reinauer <[email protected]> Modified: trunk/src/Kconfig.deprecated_options trunk/src/arch/x86/boot/coreboot_table.c trunk/src/arch/x86/include/arch/interrupt.h trunk/src/devices/oprom/yabel/device.c trunk/src/devices/oprom/yabel/interrupt.c trunk/src/devices/oprom/yabel/io.c trunk/src/devices/oprom/yabel/mem.c trunk/src/devices/pci_rom.c trunk/src/devices/pciexp_device.c trunk/src/include/cpu/x86/mtrr.h trunk/src/mainboard/kontron/986lcd-m/mainboard.c trunk/src/northbridge/intel/i82830/smihandler.c trunk/src/northbridge/intel/i82830/vga.c trunk/src/northbridge/intel/i945/raminit.c trunk/src/southbridge/via/k8t890/early_car.c trunk/src/southbridge/via/vt8237r/lpc.c trunk/src/superio/ite/it8716f/it8716f.h trunk/src/superio/ite/it8716f/superio.c Modified: trunk/src/Kconfig.deprecated_options ============================================================================== --- trunk/src/Kconfig.deprecated_options Thu Apr 21 00:23:56 2011 (r6534) +++ trunk/src/Kconfig.deprecated_options Thu Apr 21 22:24:43 2011 (r6535) @@ -51,4 +51,14 @@ this option, then you can say N here to speed up boot time. Otherwise say Y. +# This was a config option for a long time, but it never showed up in Kconfig. +# It should go away and "tuning" should always be enabled when PCIe is there, +# or it should be more fine grained (ie. Enable PCIe ASPM) +config PCIE_TUNING + bool + default n + help + This variable enables certain PCIe optimizations. Right now it's + only ASPM and it's untested. + endmenu Modified: trunk/src/arch/x86/boot/coreboot_table.c ============================================================================== --- trunk/src/arch/x86/boot/coreboot_table.c Thu Apr 21 00:23:56 2011 (r6534) +++ trunk/src/arch/x86/boot/coreboot_table.c Thu Apr 21 22:24:43 2011 (r6535) @@ -145,7 +145,7 @@ static void lb_framebuffer(struct lb_header *header) { -#if defined(CONFIG_BOOTSPLASH) && CONFIG_BOOTSPLASH && CONFIG_COREBOOT_KEEP_FRAMEBUFFER +#if CONFIG_BOOTSPLASH && CONFIG_COREBOOT_KEEP_FRAMEBUFFER void fill_lb_framebuffer(struct lb_framebuffer *framebuffer); struct lb_framebuffer *framebuffer; Modified: trunk/src/arch/x86/include/arch/interrupt.h ============================================================================== --- trunk/src/arch/x86/include/arch/interrupt.h Thu Apr 21 00:23:56 2011 (r6534) +++ trunk/src/arch/x86/include/arch/interrupt.h Thu Apr 21 22:24:43 2011 (r6535) @@ -22,7 +22,7 @@ #include "registers.h" /* setup interrupt handlers for mainboard */ -#if defined(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) && CONFIG_PCI_OPTION_ROM_RUN_REALMODE +#if CONFIG_PCI_OPTION_ROM_RUN_REALMODE extern void mainboard_interrupt_handlers(int intXX, void *intXX_func); #else static inline void mainboard_interrupt_handlers(int intXX, void *intXX_func) { } Modified: trunk/src/devices/oprom/yabel/device.c ============================================================================== --- trunk/src/devices/oprom/yabel/device.c Thu Apr 21 00:23:56 2011 (r6534) +++ trunk/src/devices/oprom/yabel/device.c Thu Apr 21 22:24:43 2011 (r6535) @@ -37,7 +37,7 @@ u64 size; } __attribute__ ((__packed__)) assigned_address_t; -#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL /* coreboot version */ static void @@ -110,7 +110,7 @@ } // store last entry index of translate_address_array taa_last_entry = taa_index - 1; -#if defined(CONFIG_X86EMU_DEBUG) && CONFIG_X86EMU_DEBUG +#if CONFIG_X86EMU_DEBUG //dump translate_address_array printf("translate_address_array: \n"); translate_address_t ta; @@ -194,7 +194,7 @@ } // store last entry index of translate_address_array taa_last_entry = taa_index - 1; -#if defined(CONFIG_X86EMU_DEBUG) && CONFIG_X86EMU_DEBUG +#if CONFIG_X86EMU_DEBUG //dump translate_address_array printf("translate_address_array: \n"); translate_address_t ta; @@ -226,7 +226,7 @@ translate_address_array[taa_index].address_offset = 0; } -#ifndef CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if !CONFIG_PCI_OPTION_ROM_RUN_YABEL // to simulate accesses to legacy VGA Memory (0xA0000-0xBFFFF) // we look for the first prefetchable memory BAR, if no prefetchable BAR found, // we use the first memory BAR @@ -288,7 +288,7 @@ { u32 pci_config_0; -#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL pci_config_0 = pci_read_config32(bios_device.dev, 0x0); #else pci_config_0 = @@ -350,7 +350,7 @@ memcpy(&pci_ds, (void *) (rom_base_addr + pci_ds_offset), sizeof(pci_ds)); clr_ci(); -#if defined(CONFIG_X86EMU_DEBUG) && CONFIG_X86EMU_DEBUG +#if CONFIG_X86EMU_DEBUG DEBUG_PRINTF("PCI Data Structure @%lx:\n", rom_base_addr + pci_ds_offset); dump((void *) &pci_ds, sizeof(pci_ds)); @@ -412,7 +412,7 @@ DEBUG_PRINTF("%s\n", __func__); memset(&bios_device, 0, sizeof(bios_device)); -#ifndef CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if !CONFIG_PCI_OPTION_ROM_RUN_YABEL bios_device.ihandle = of_open(device_name); if (bios_device.ihandle == 0) { DEBUG_PRINTF("%s is no valid device!\n", device_name); @@ -423,7 +423,7 @@ bios_device.dev = device; #endif biosemu_dev_get_addr_info(); -#ifndef CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if !CONFIG_PCI_OPTION_ROM_RUN_YABEL biosemu_dev_find_vmem_addr(); biosemu_dev_get_puid(); #endif @@ -440,7 +440,7 @@ { int i = 0; translate_address_t ta; -#ifndef CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if !CONFIG_PCI_OPTION_ROM_RUN_YABEL /* we dont need this hack for coreboot... we can access legacy areas */ //check if it is an access to legacy VGA Mem... if it is, map the address //to the vmem BAR and then translate it... Modified: trunk/src/devices/oprom/yabel/interrupt.c ============================================================================== --- trunk/src/devices/oprom/yabel/interrupt.c Thu Apr 21 00:23:56 2011 (r6534) +++ trunk/src/devices/oprom/yabel/interrupt.c Thu Apr 21 22:24:43 2011 (r6535) @@ -24,7 +24,7 @@ #include <x86emu/x86emu.h> #include "../x86emu/prim_ops.h" -#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL #include <device/pci.h> #include <device/pci_ops.h> #endif @@ -343,7 +343,7 @@ DEBUG_PRINTF_INTR("%s(): function: %x: PCI Find Device\n", __func__, M.x86.R_AX); /* FixME: support SI != 0 */ -#if defined(CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES) && CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES==1 +#if CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES dev = dev_find_device(M.x86.R_DX, M.x86.R_CX, 0); if (dev != 0) { DEBUG_PRINTF_INTR @@ -384,7 +384,7 @@ offs = M.x86.R_DI; DEBUG_PRINTF_INTR("%s(): function: %x: PCI Config Read from device: bus: %02x, devfn: %02x, offset: %02x\n", __func__, M.x86.R_AX, bus, devfn, offs); -#if defined(CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES) && CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES==1 +#if CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES dev = dev_find_slot(bus, devfn); DEBUG_PRINTF_INTR("%s(): function: %x: dev_find_slot() returned: %s\n", __func__, M.x86.R_AX, dev_path(dev)); @@ -408,7 +408,7 @@ switch (M.x86.R_AX) { case 0xb108: M.x86.R_CL = -#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL pci_read_config8(dev, offs); #else (u8) rtas_pci_config_read(bios_device. @@ -423,7 +423,7 @@ break; case 0xb109: M.x86.R_CX = -#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL pci_read_config16(dev, offs); #else (u16) rtas_pci_config_read(bios_device. @@ -438,7 +438,7 @@ break; case 0xb10a: M.x86.R_ECX = -#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL pci_read_config32(dev, offs); #else (u32) rtas_pci_config_read(bios_device. @@ -476,7 +476,7 @@ } else { switch (M.x86.R_AX) { case 0xb10b: -#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL pci_write_config8(bios_device.dev, offs, M.x86.R_CL); #else rtas_pci_config_write(bios_device.puid, 1, bus, @@ -488,7 +488,7 @@ M.x86.R_CL); break; case 0xb10c: -#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL pci_write_config16(bios_device.dev, offs, M.x86.R_CX); #else rtas_pci_config_write(bios_device.puid, 2, bus, @@ -500,7 +500,7 @@ M.x86.R_CX); break; case 0xb10d: -#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL pci_write_config32(bios_device.dev, offs, M.x86.R_ECX); #else rtas_pci_config_write(bios_device.puid, 4, bus, @@ -576,8 +576,9 @@ int_handled = 1; break; case PMM_INT_NUM: - /* the selfdefined PMM INT number, this is called by the code in PMM struct, it - * is handled by pmm_handleInt() + /* The self-defined PMM INT number, this is called by + * the code in PMM struct, and it is handled by + * pmm_handleInt() */ pmm_handleInt(); int_handled = 1; Modified: trunk/src/devices/oprom/yabel/io.c ============================================================================== --- trunk/src/devices/oprom/yabel/io.c Thu Apr 21 00:23:56 2011 (r6534) +++ trunk/src/devices/oprom/yabel/io.c Thu Apr 21 22:24:43 2011 (r6535) @@ -19,13 +19,13 @@ #include <x86emu/x86emu.h> #include "io.h" -#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL #include <device/pci.h> #include <device/pci_ops.h> #include <device/resource.h> #endif -#ifdef CONFIG_ARCH_X86 +#if CONFIG_ARCH_X86 #include <arch/io.h> #else // these are not used, only needed for linking, must be overridden using X86emu_setupPioFuncs @@ -76,7 +76,7 @@ } #endif -#if defined(CONFIG_YABEL_DIRECTHW) && (CONFIG_YABEL_DIRECTHW == 1) +#if CONFIG_YABEL_DIRECTHW u8 my_inb(X86EMU_pioAddr addr) { u8 val; @@ -455,7 +455,7 @@ offs += (addr - 0xCFC); // if addr is not 0xcfc, the offset is moved accordingly DEBUG_PRINTF_INTR("%s(): PCI Config Read from device: bus: %02x, devfn: %02x, offset: %02x\n", __func__, bus, devfn, offs); -#if defined(CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES) && CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES==1 +#if CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES dev = dev_find_slot(bus, devfn); DEBUG_PRINTF_INTR("%s(): dev_find_slot() returned: %s\n", __func__, dev_path(dev)); @@ -475,7 +475,7 @@ HALT_SYS(); return 0; } else { -#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL switch (size) { case 1: rval = pci_read_config8(dev, offs); @@ -526,7 +526,7 @@ bus, devfn >> 3, devfn & 7, offs); HALT_SYS(); } else { -#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL switch (size) { case 1: pci_write_config8(bios_device.dev, offs, val); Modified: trunk/src/devices/oprom/yabel/mem.c ============================================================================== --- trunk/src/devices/oprom/yabel/mem.c Thu Apr 21 00:23:56 2011 (r6534) +++ trunk/src/devices/oprom/yabel/mem.c Thu Apr 21 22:24:43 2011 (r6535) @@ -19,9 +19,9 @@ #include "mem.h" #include "compat/time.h" -#if !defined(CONFIG_YABEL_DIRECTHW) || (!CONFIG_YABEL_DIRECTHW) +#if !CONFIG_YABEL_DIRECTHW || !CONFIG_YABEL_DIRECTHW -#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL #include <device/resource.h> #endif Modified: trunk/src/devices/pci_rom.c ============================================================================== --- trunk/src/devices/pci_rom.c Thu Apr 21 00:23:56 2011 (r6534) +++ trunk/src/devices/pci_rom.c Thu Apr 21 22:24:43 2011 (r6535) @@ -46,7 +46,7 @@ rom_address = pci_read_config32(dev, PCI_ROM_ADDRESS); if (rom_address == 0x00000000 || rom_address == 0xffffffff) { -#if defined(CONFIG_BOARD_EMULATION_QEMU_X86) && CONFIG_BOARD_EMULATION_QEMU_X86 +#if CONFIG_BOARD_EMULATION_QEMU_X86 if ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA) rom_address = 0xc0000; else Modified: trunk/src/devices/pciexp_device.c ============================================================================== --- trunk/src/devices/pciexp_device.c Thu Apr 21 00:23:56 2011 (r6534) +++ trunk/src/devices/pciexp_device.c Thu Apr 21 22:24:43 2011 (r6535) @@ -27,7 +27,7 @@ static void pciexp_tune_dev(device_t dev) { unsigned int cap; -#ifdef CONFIG_PCIE_TUNING +#if CONFIG_PCIE_TUNING u32 reg32; #endif @@ -35,7 +35,7 @@ if (!cap) return; -#ifdef CONFIG_PCIE_TUNING +#if CONFIG_PCIE_TUNING printk(BIOS_DEBUG, "PCIe: tuning %s\n", dev_path(dev)); // TODO make this depending on ASPM. Modified: trunk/src/include/cpu/x86/mtrr.h ============================================================================== --- trunk/src/include/cpu/x86/mtrr.h Thu Apr 21 00:23:56 2011 (r6534) +++ trunk/src/include/cpu/x86/mtrr.h Thu Apr 21 22:24:43 2011 (r6535) @@ -1,7 +1,6 @@ #ifndef CPU_X86_MTRR_H #define CPU_X86_MTRR_H - /* These are the region types */ #define MTRR_TYPE_UNCACHEABLE 0 #define MTRR_TYPE_WRCOMB 1 @@ -64,11 +63,10 @@ # error "CONFIG_XIP_ROM_BASE is not a multiple of CONFIG_XIP_ROM_SIZE" #endif -#if (CONFIG_RAMTOP & (CONFIG_RAMTOP -1)) != 0 +#if (CONFIG_RAMTOP & (CONFIG_RAMTOP - 1)) != 0 # error "CONFIG_RAMTOP must be a power of 2" #endif - #if !defined (__ASSEMBLER__) #if defined(CONFIG_XIP_ROM_SIZE) # if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK Modified: trunk/src/mainboard/kontron/986lcd-m/mainboard.c ============================================================================== --- trunk/src/mainboard/kontron/986lcd-m/mainboard.c Thu Apr 21 00:23:56 2011 (r6534) +++ trunk/src/mainboard/kontron/986lcd-m/mainboard.c Thu Apr 21 22:24:43 2011 (r6535) @@ -20,14 +20,14 @@ #include <types.h> #include <device/device.h> #include <console/console.h> -#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL #include <x86emu/x86emu.h> #endif #include <pc80/mc146818rtc.h> #include <arch/io.h> #include "chip.h" -#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL static int int15_handler(void) { #define BOOT_DISPLAY_DEFAULT 0 @@ -221,7 +221,7 @@ static void mainboard_enable(device_t dev) { -#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL /* Install custom int15 handler for VGA OPROM */ int15_install(); #endif Modified: trunk/src/northbridge/intel/i82830/smihandler.c ============================================================================== --- trunk/src/northbridge/intel/i82830/smihandler.c Thu Apr 21 00:23:56 2011 (r6534) +++ trunk/src/northbridge/intel/i82830/smihandler.c Thu Apr 21 22:24:43 2011 (r6535) @@ -37,7 +37,7 @@ /* If YABEL is enabled and it's not running at 0x00000000, we have to add some * offset to all our mbi object memory accesses */ -#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL && !CONFIG_YABEL_DIRECTHW +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL && !CONFIG_YABEL_DIRECTHW #define OBJ_OFFSET CONFIG_YABEL_VIRTMEM_LOCATION #else #define OBJ_OFFSET 0x00000 Modified: trunk/src/northbridge/intel/i82830/vga.c ============================================================================== --- trunk/src/northbridge/intel/i82830/vga.c Thu Apr 21 00:23:56 2011 (r6534) +++ trunk/src/northbridge/intel/i82830/vga.c Thu Apr 21 22:24:43 2011 (r6535) @@ -25,7 +25,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <cbfs.h> -#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL #include <x86emu/x86emu.h> #endif @@ -62,7 +62,7 @@ printk(BIOS_INFO, "Graphics Initialization Complete\n"); /* Enable TV-Out */ -#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL #define PIPE_A_CRT (1 << 0) #define PIPE_A_LFP (1 << 1) #define PIPE_A_TV (1 << 3) Modified: trunk/src/northbridge/intel/i945/raminit.c ============================================================================== --- trunk/src/northbridge/intel/i945/raminit.c Thu Apr 21 00:23:56 2011 (r6534) +++ trunk/src/northbridge/intel/i945/raminit.c Thu Apr 21 22:24:43 2011 (r6535) @@ -113,7 +113,7 @@ static int memclk(void) { int offset = 0; -#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM) +#if CONFIG_NORTHBRIDGE_INTEL_I945GM offset++; #endif switch (((MCHBAR32(CLKCFG) >> 4) & 7) - offset) { @@ -125,7 +125,7 @@ return -1; } -#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM) +#if CONFIG_NORTHBRIDGE_INTEL_I945GM static u16 fsbclk(void) { switch (MCHBAR32(CLKCFG) & 7) { @@ -136,7 +136,7 @@ } return 0xffff; } -#elif defined(CONFIG_NORTHBRIDGE_INTEL_I945GC) +#elif CONFIG_NORTHBRIDGE_INTEL_I945GC static u16 fsbclk(void) { switch (MCHBAR32(CLKCFG) & 7) { @@ -1075,7 +1075,7 @@ return nc; } -#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM) +#if CONFIG_NORTHBRIDGE_INTEL_I945GM /* Strength multiplier tables */ static const u8 dual_channel_strength_multiplier[] = { 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11, @@ -1130,7 +1130,7 @@ 0x33, 0x00, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11, 0x33, 0x00, 0x11, 0x00, 0x44, 0x44, 0x33, 0x11 }; -#elif defined(CONFIG_NORTHBRIDGE_INTEL_I945GC) +#elif CONFIG_NORTHBRIDGE_INTEL_I945GC static const u8 dual_channel_strength_multiplier[] = { 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, @@ -2186,7 +2186,7 @@ /** * We add the indices according to our clocks from CLKCFG. */ -#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM) +#if CONFIG_NORTHBRIDGE_INTEL_I945GM static const u32 data_clock_crossing[] = { 0x00100401, 0x00000000, /* DDR400 FSB400 */ 0xffffffff, 0xffffffff, /* nonexistant */ @@ -2231,7 +2231,7 @@ 0xffffffff, 0xffffffff, /* nonexistant */ }; -#elif defined(CONFIG_NORTHBRIDGE_INTEL_I945GC) +#elif CONFIG_NORTHBRIDGE_INTEL_I945GC /* i945 G/P */ static const u32 data_clock_crossing[] = { 0xffffffff, 0xffffffff, /* nonexistant */ @@ -2822,9 +2822,9 @@ { u8 clocks[2] = { 0, 0 }; -#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM) +#if CONFIG_NORTHBRIDGE_INTEL_I945GM #define CLOCKS_WIDTH 2 -#elif defined(CONFIG_NORTHBRIDGE_INTEL_I945GC) +#elif CONFIG_NORTHBRIDGE_INTEL_I945GC #define CLOCKS_WIDTH 3 #endif if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED) Modified: trunk/src/southbridge/via/k8t890/early_car.c ============================================================================== --- trunk/src/southbridge/via/k8t890/early_car.c Thu Apr 21 00:23:56 2011 (r6534) +++ trunk/src/southbridge/via/k8t890/early_car.c Thu Apr 21 22:24:43 2011 (r6535) @@ -69,15 +69,15 @@ ldtnr = 2; } -#if defined(CONFIG_SOUTHBRIDGE_VIA_K8M800) +#if CONFIG_SOUTHBRIDGE_VIA_K8M800 print_debug("K8M800 found at LDT "); -#elif defined(CONFIG_SOUTHBRIDGE_VIA_K8T800) +#elif CONFIG_SOUTHBRIDGE_VIA_K8T800 print_debug("K8T800 found at LDT "); -#elif defined(CONFIG_SOUTHBRIDGE_VIA_K8T800PRO) +#elif CONFIG_SOUTHBRIDGE_VIA_K8T800PRO print_debug("K8T800 Pro found at LDT "); -#elif defined(CONFIG_SOUTHBRIDGE_VIA_K8M890) +#elif CONFIG_SOUTHBRIDGE_VIA_K8M890 print_debug("K8M890 found at LDT "); -#elif defined(CONFIG_SOUTHBRIDGE_VIA_K8T890) +#elif CONFIG_SOUTHBRIDGE_VIA_K8T890 print_debug("K8T890 found at LDT "); #endif print_debug_hex8(ldtnr); Modified: trunk/src/southbridge/via/vt8237r/lpc.c ============================================================================== --- trunk/src/southbridge/via/vt8237r/lpc.c Thu Apr 21 00:23:56 2011 (r6534) +++ trunk/src/southbridge/via/vt8237r/lpc.c Thu Apr 21 22:24:43 2011 (r6535) @@ -300,7 +300,7 @@ pci_write_config8(dev, 0x48, 0x0c); #else - #if defined(CONFIG_SOUTHBRIDGE_VIA_K8T800) + #if CONFIG_SOUTHBRIDGE_VIA_K8T800 /* It seems that when we pair with the K8T800, we need to disable * the A2 mask */ Modified: trunk/src/superio/ite/it8716f/it8716f.h ============================================================================== --- trunk/src/superio/ite/it8716f/it8716f.h Thu Apr 21 00:23:56 2011 (r6534) +++ trunk/src/superio/ite/it8716f/it8716f.h Thu Apr 21 22:24:43 2011 (r6535) @@ -36,7 +36,7 @@ #define IT8716F_GAME 0x09 /* GAME port */ #define IT8716F_IR 0x0a /* Consumer IR */ -#if defined(CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL) && CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL +#if CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL /* Provided by mainboard, called by IT8716F superio.c. */ void init_ec(u16 base); #endif Modified: trunk/src/superio/ite/it8716f/superio.c ============================================================================== --- trunk/src/superio/ite/it8716f/superio.c Thu Apr 21 00:23:56 2011 (r6534) +++ trunk/src/superio/ite/it8716f/superio.c Thu Apr 21 22:24:43 2011 (r6535) @@ -46,7 +46,7 @@ pnp_write_config(dev, 0x02, 0x02); } -#if !defined(CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL) || !CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL +#if !CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL static void pnp_write_index(u16 port_base, u8 reg, u8 value) { outb(reg, port_base); -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
