this patch switch to use the sb800 old lib code.
Index: src/vendorcode/amd/cimx/lib/amdlib32.h
===================================================================
--- src/vendorcode/amd/cimx/lib/amdlib32.h	(revision 0)
+++ src/vendorcode/amd/cimx/lib/amdlib32.h	(revision 0)
@@ -0,0 +1,16 @@
+#ifndef _AMDLIB32_H_
+#define _AMDLIB32_H_
+
+#include "cbtypes.h"
+#include "Amd.h"
+
+UINT8 ReadIo8 (IN UINT16 port);
+UINT16 ReadIo16 (IN UINT16 port);
+UINT32 ReadIo32 (IN UINT16 port);
+VOID WriteIo8 (IN UINT16 port, IN UINT8 value);
+VOID WriteIo16 (IN UINT16 port, IN UINT16 value);
+VOID WriteIo32 (IN UINT16 port, IN UINT32 value);
+UINT64 ReadTSC(VOID);
+VOID CpuidRead(IN UINT32 op, IN OUT CPUID_DATA* Data);
+UINT8 ReadNumberOfCpuCores(VOID);
+#endif //_AMDLIB32_H_
Index: src/vendorcode/amd/cimx/lib/Makefile.inc
===================================================================
--- src/vendorcode/amd/cimx/lib/Makefile.inc	(revision 0)
+++ src/vendorcode/amd/cimx/lib/Makefile.inc	(revision 0)
@@ -0,0 +1,3 @@
+
+romstage-y += amdlib32.c
+ramstage-y += amdlib32.c
Index: src/vendorcode/amd/cimx/lib/amdlib32.c
===================================================================
--- src/vendorcode/amd/cimx/lib/amdlib32.c	(revision 0)
+++ src/vendorcode/amd/cimx/lib/amdlib32.c	(revision 0)
@@ -0,0 +1,84 @@
+#include "amdlib32.h"
+
+UINT8 ReadIo8 (IN UINT16 port)
+{
+	UINT8 value;
+	__asm__ __volatile__ ("inb %w1, %b0" : "=a"(value) : "Nd" (port));
+	return value;
+}
+
+UINT16 ReadIo16 (IN UINT16 port)
+{
+        UINT16 value;
+        __asm__ __volatile__ ("inw %w1, %w0" : "=a"(value) : "Nd" (port));
+        return value;
+}
+
+UINT32 ReadIo32 (IN UINT16 port)
+{
+        UINT32 value;
+        __asm__ __volatile__ ("inl %w1, %0" : "=a"(value) : "Nd" (port));
+        return value;
+}
+
+VOID WriteIo8 (IN UINT16 port, IN UINT8 value)
+{
+        __asm__ __volatile__ ("outb %b0, %w1" : : "a" (value), "Nd" (port));
+}
+
+VOID WriteIo16 (IN UINT16 port, IN UINT16 value)
+{
+        __asm__ __volatile__ ("outw %w0, %w1" : : "a" (value), "Nd" (port));
+}
+
+VOID WriteIo32 (IN UINT16 port, IN UINT32 value)
+{
+        __asm__ __volatile__ ("outl %0, %w1" : : "a" (value), "Nd" (port));
+}
+
+UINT64 ReadTSC(VOID)
+{
+	struct tsc_struct {
+		unsigned lo;
+		unsigned hi;
+	} res;
+	UINT64 ret;
+
+	__asm__ __volatile__ (
+			"rdtsc" 
+			: "=a" (res.lo), "=d"(res.hi) /* outputs */
+			);
+	ret = res.hi;
+	ret <<= 32;
+	ret |= res.lo;
+	return ret;
+}
+
+VOID CpuidRead(IN UINT32 op, IN OUT CPUID_DATA* Data)
+{
+        asm volatile(
+                "cpuid"
+                : "=a" (Data->EAX_Reg),
+                  "=b" (Data->EBX_Reg),
+                  "=c" (Data->ECX_Reg),
+                  "=d" (Data->EDX_Reg)
+                : "0" (op));
+}
+
+static inline unsigned int cpuid_ecx(unsigned int op)
+{
+        unsigned int eax, ecx;
+
+        __asm__("cpuid"
+                : "=a" (eax), "=c" (ecx)
+                : "0" (op)
+                : "ebx", "edx" );
+        return ecx;
+}
+
+//static inline unsigned get_core_num(void)
+UINT8 ReadNumberOfCpuCores(VOID)
+{
+        return (cpuid_ecx(0x80000008) & 0xff);
+}
+
Index: src/mainboard/advansus/a785e-i/Makefile.inc
===================================================================
--- src/mainboard/advansus/a785e-i/Makefile.inc	(revision 1168)
+++ src/mainboard/advansus/a785e-i/Makefile.inc	(working copy)
@@ -5,17 +5,14 @@
 ramstage-y += pmio.c
 ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c
 
+subdirs-y += ../../../../src/vendorcode/amd/cimx/lib
 #SB800 CIMx share AGESA V5 lib code
 ifneq ($(CONFIG_AMD_AGESA),y)