Hello,
I wrote a blog post about this:
http://blogs.coreboot.org/blog/2011/04/30/u-boot-as-coreboot-payload/
I'm attaching patches so you see what I have right now. Please consider them
just a "test" I did not change the copyrights etc. Maybe they are just a big
mess. Maybe you find them useful.
The current problems are:
1) I have PCI resource conflicts with QEMU and coreboot
This is just now a showstopper. Definetely no time to investigate right now/
2) I have in plan to get rid of u-boot relocation by relocating it exactly 0
bytes ;)
3) I still don't know git despite F1 from Carebear ;)
Thanks,
Rudolf
>From d571c02e5c831e70cccec23392ff41946d9d7111 Mon Sep 17 00:00:00 2001
From: marekr2 <marekr2@kiur.(none)>
Date: Mon, 25 Apr 2011 20:44:45 +0200
Subject: [PATCH 1/2] both
first try
add more
---
arch/x86/cpu/config.mk | 4 +-
arch/x86/cpu/coreboot/Makefile | 58 ++++
arch/x86/cpu/coreboot/coreboot_car.S | 35 ++
arch/x86/cpu/coreboot/pci.c | 71 ++++
arch/x86/cpu/coreboot/sdram.c | 65 ++++
arch/x86/cpu/interrupts.c | 87 +++++
arch/x86/lib/realmode.c | 3 -
board/coreboot/Makefile | 58 ++++
board/coreboot/coreboot.c | 100 ++++++
board/coreboot/coreboot_pci.c | 76 +++++
board/coreboot/coreboot_start.S | 30 ++
board/coreboot/coreboot_start16.S | 51 +++
board/coreboot/hardware.h | 28 ++
boards.cfg | 3 +-
build | 3 +
common/serial.c | 2 +-
include/configs/coreboot.h | 618 ++++++++++++++++++++++++++++++++++
include/serial.h | 2 +-
wrap.asm | 4 +
19 files changed, 1290 insertions(+), 8 deletions(-)
create mode 100644 arch/x86/cpu/coreboot/Makefile
create mode 100644 arch/x86/cpu/coreboot/coreboot_car.S
create mode 100644 arch/x86/cpu/coreboot/pci.c
create mode 100644 arch/x86/cpu/coreboot/sdram.c
create mode 100644 board/coreboot/Makefile
create mode 100644 board/coreboot/coreboot.c
create mode 100644 board/coreboot/coreboot_pci.c
create mode 100644 board/coreboot/coreboot_start.S
create mode 100644 board/coreboot/coreboot_start16.S
create mode 100644 board/coreboot/hardware.h
create mode 100644 build
create mode 100644 include/configs/coreboot.h
create mode 100644 wrap.asm
diff --git a/arch/x86/cpu/config.mk b/arch/x86/cpu/config.mk
index d1b528a..3cae615 100644
--- a/arch/x86/cpu/config.mk
+++ b/arch/x86/cpu/config.mk
@@ -23,10 +23,10 @@
CROSS_COMPILE ?= i386-linux-
-PLATFORM_CPPFLAGS += -DCONFIG_X86 -D__I386__ -march=i386 -Werror
+PLATFORM_CPPFLAGS += -DCONFIG_X86 -D__I386__ -march=i386
# DO NOT MODIFY THE FOLLOWING UNLESS YOU REALLY KNOW WHAT YOU ARE DOING!
-LDPPFLAGS += -DRESET_SEG_START=0xffff0000
+LDPPFLAGS += -DRESET_SEG_START=0xFF0000
LDPPFLAGS += -DRESET_SEG_SIZE=0x10000
LDPPFLAGS += -DRESET_VEC_LOC=0xfff0
LDPPFLAGS += -DSTART_16=0xf800
diff --git a/arch/x86/cpu/coreboot/Makefile b/arch/x86/cpu/coreboot/Makefile
new file mode 100644
index 0000000..bdc244f
--- /dev/null
+++ b/arch/x86/cpu/coreboot/Makefile
@@ -0,0 +1,58 @@
+#
+# (C) Copyright 2008
+# Graeme Russ, [email protected].
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, [email protected].
+#
+# (C) Copyright 2002
+# Daniel Engström, Omicron Ceti AB, [email protected].
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB := $(obj)lib$(SOC).o
+
+#COBJS-$(CONFIG_SYS_SC520) += sc520.o
+COBJS-$(CONFIG_PCI) += pci.o
+#COBJS-$(CONFIG_SYS_SC520_RESET) += sc520_reset.o
+COBJS-$(CONFIG_SYS_COREBOOT) += sdram.o
+#COBJS-$(CONFIG_SYS_SC520_SSI) += sc520_ssi.o
+#COBJS-$(CONFIG_SYS_SC520_TIMER) += sc520_timer.o
+
+SOBJS-$(CONFIG_SYS_COREBOOT) += coreboot_car.o
+
+SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
\ No newline at end of file
diff --git a/arch/x86/cpu/coreboot/coreboot_car.S b/arch/x86/cpu/coreboot/coreboot_car.S
new file mode 100644
index 0000000..1409f67
--- /dev/null
+++ b/arch/x86/cpu/coreboot/coreboot_car.S
@@ -0,0 +1,35 @@
+/*
+ * (C) Copyright 2010-2011
+ * Graeme Russ, <[email protected]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/processor-flags.h>
+
+.section .text
+
+.globl car_init
+car_init:
+ /*
+ * Done - We should now have CONFIG_SYS_CAR_SIZE bytes of
+ * Cache-As-RAM
+ */
+ jmp car_init_ret
diff --git a/arch/x86/cpu/coreboot/pci.c b/arch/x86/cpu/coreboot/pci.c
new file mode 100644
index 0000000..2c860c8
--- /dev/null
+++ b/arch/x86/cpu/coreboot/pci.c
@@ -0,0 +1,71 @@
+/*
+ * (C) Copyright 2008-2011
+ * Graeme Russ, <[email protected]>
+ *
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB, <[email protected]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/io.h>
+#include <asm/pci.h>
+
+/* utility function to configure a pci interrupt */
+int pci_sc520_set_irq(int pci_pin, int irq)
+{
+ int i;
+ u8 tmpb;
+ u16 tmpw;
+
+ debug("set_irq(): map INT%c to IRQ%d\n", pci_pin + 'A', irq);
+
+ if (irq < 0 || irq > 15) {
+ return -1; /* illegal irq */
+ }
+
+ if (pci_pin < 0 || pci_pin > 15) {
+ return -1; /* illegal pci int pin */
+ }
+
+ /* first disable any non-pci interrupt source that use
+ * this level */
+
+
+ return 0; /* OK */
+}
+
+void pci_sc520_init(struct pci_controller *hose)
+{
+ hose->first_busno = 0;
+ hose->last_busno = 0xff;
+ hose->region_count = pci_set_regions(hose);
+
+ pci_setup_type1(hose, 0xcf8, 0xcfc);
+
+ pci_register_hose(hose);
+
+ hose->last_busno = pci_hose_scan(hose);
+
+ /* enable target memory acceses on host brige */
+ pci_write_config_word(0, PCI_COMMAND,
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+}
diff --git a/arch/x86/cpu/coreboot/sdram.c b/arch/x86/cpu/coreboot/sdram.c
new file mode 100644
index 0000000..a552f0e
--- /dev/null
+++ b/arch/x86/cpu/coreboot/sdram.c
@@ -0,0 +1,65 @@
+/*
+ * (C) Copyright 2010,2011
+ * Graeme Russ, <[email protected]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/processor-flags.h>
+#include <asm/ic/sc520.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct sc520_sdram_info {
+ u8 banks;
+ u8 columns;
+ u8 rows;
+ u8 size;
+};
+
+static void sc520_sizemem(void);
+static void sc520_set_dram_timing(void);
+static void sc520_set_dram_refresh_rate(void);
+static void sc520_enable_dram_refresh(void);
+static void sc520_enable_sdram(void);
+#if CONFIG_SYS_SDRAM_ECC_ENABLE
+static void sc520_enable_ecc(void)
+#endif
+
+int dram_init_f(void) {
+ gd->ram_size = 64*1024*1024;
+
+ return 0;
+}
+
+
+int dram_init(void)
+{
+ ulong dram_ctrl;
+ ulong dram_present = 0x00000000;
+
+
+ gd->bd->bi_dram[0].start = 0;
+ gd->bd->bi_dram[0].size = 64*1024*1024;
+
+
+ return 0;
+}
diff --git a/arch/x86/cpu/interrupts.c b/arch/x86/cpu/interrupts.c
index 62bcadc..4405cd1 100644
--- a/arch/x86/cpu/interrupts.c
+++ b/arch/x86/cpu/interrupts.c
@@ -190,6 +190,87 @@ void set_vector(u8 intnum, void *routine)
void irq_0(void);
void irq_1(void);
+#define MASTER_PIC_ICW1 0x20
+#define SLAVE_PIC_ICW1 0xa0
+#define ICW_SELECT (1 << 4)
+#define OCW_SELECT (0 << 4)
+#define ADI (1 << 2)
+#define SNGL (1 << 1)
+#define IC4 (1 << 0)
+
+#define MASTER_PIC_ICW2 0x21
+#define SLAVE_PIC_ICW2 0xa1
+#define INT_VECTOR_MASTER 0x20
+#define IRQ0 0x00
+#define IRQ1 0x01
+#define INT_VECTOR_SLAVE 0x28
+#define IRQ8 0x00
+#define IRQ9 0x01
+
+#define MASTER_PIC_ICW3 0x21
+#define CASCADED_PIC (1 << 2)
+
+#define MASTER_PIC_ICW4 0x21
+#define SLAVE_PIC_ICW4 0xa1
+#define MICROPROCESSOR_MODE (1 << 0)
+
+#define SLAVE_PIC_ICW3 0xa1
+#define SLAVE_ID 0x02
+
+#define MASTER_PIC_OCW1 0x21
+#define SLAVE_PIC_OCW1 0xa1
+#define IRQ2 (1 << 2)
+#define ALL_IRQS 0xff
+
+#define ELCR1 0x4d0
+#define ELCR2 0x4d1
+
+void setup_i8259(void)
+{
+ /* A write to ICW1 starts the Interrupt Controller Initialization
+ * Sequence. This implicitly causes the following to happen:
+ * - Interrupt Mask register is cleared
+ * - Priority 7 is assigned to IRQ7 input
+ * - Slave mode address is set to 7
+ * - Special mask mode is cleared
+ *
+ * We send the initialization sequence to both the master and
+ * slave i8259 controller.
+ */
+ outb(ICW_SELECT|IC4, MASTER_PIC_ICW1);
+ outb(ICW_SELECT|IC4, SLAVE_PIC_ICW1);
+
+ /* Now the interrupt controller expects us to write to ICW2. */
+ outb(INT_VECTOR_MASTER | IRQ0, MASTER_PIC_ICW2);
+ outb(INT_VECTOR_SLAVE | IRQ8, SLAVE_PIC_ICW2);
+
+ /* Now the interrupt controller expects us to write to ICW3.
+ *
+ * The normal scenario is to set up cascading on IRQ2 on the master
+ * i8259 and assign the slave ID 2 to the slave i8259.
+ */
+ outb(CASCADED_PIC, MASTER_PIC_ICW3);
+ outb(SLAVE_ID, SLAVE_PIC_ICW3);
+
+ /* Now the interrupt controller expects us to write to ICW4.
+ *
+ * We switch both i8259 to microprocessor mode because they're
+ * operating as part of an x86 architecture based chipset
+ */
+ outb(MICROPROCESSOR_MODE, MASTER_PIC_ICW2);
+ outb(MICROPROCESSOR_MODE, SLAVE_PIC_ICW2);
+
+ /* Now clear the interrupts through OCW1.
+ * First we mask off all interrupts on the slave interrupt controller
+ * then we mask off all interrupts but interrupt 2 on the master
+ * controller. This way the cascading stays alife.
+ */
+ outb(ALL_IRQS, SLAVE_PIC_OCW1);
+ outb(ALL_IRQS & ~IRQ2, MASTER_PIC_OCW1);
+}
+
+#include <asm/i8259.h>
+
int cpu_init_interrupts(void)
{
int i;
@@ -197,9 +278,15 @@ int cpu_init_interrupts(void)
int irq_entry_size = irq_1 - irq_0;
void *irq_entry = (void *)irq_0;
+ /* Mask all interrupts */
+// outb(0xff, MASTER_PIC + IMR);
+// outb(0xff, SLAVE_PIC + IMR);
+
/* Just in case... */
disable_interrupts();
+ setup_i8259();
+
/* Setup the IDT */
for (i=0;i<256;i++) {
idt[i].access = 0x8e;
diff --git a/arch/x86/lib/realmode.c b/arch/x86/lib/realmode.c
index 5be827c..e518188 100644
--- a/arch/x86/lib/realmode.c
+++ b/arch/x86/lib/realmode.c
@@ -39,9 +39,6 @@ int realmode_setup(void)
/* copy the realmode switch code */
if (realmode_size > (REALMODE_MAILBOX - (char *)REALMODE_BASE)) {
- printf("realmode switch too large (%ld bytes, max is %d)\n",
- realmode_size,
- (REALMODE_MAILBOX - (char *)REALMODE_BASE));
return -1;
}
diff --git a/board/coreboot/Makefile b/board/coreboot/Makefile
new file mode 100644
index 0000000..fd1a40b
--- /dev/null
+++ b/board/coreboot/Makefile
@@ -0,0 +1,58 @@
+#
+# (C) Copyright 2008
+# Graeme Russ, [email protected].
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, [email protected].
+#
+# (C) Copyright 2002
+# Daniel Engström, Omicron Ceti AB, [email protected].
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS-y += coreboot.o
+COBJS-$(CONFIG_PCI) += coreboot_pci.o
+SOBJS-y += coreboot_start16.o
+SOBJS-y += coreboot_start.o
+
+SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/coreboot/coreboot.c b/board/coreboot/coreboot.c
new file mode 100644
index 0000000..5a8369b
--- /dev/null
+++ b/board/coreboot/coreboot.c
@@ -0,0 +1,100 @@
+/*
+ * (C) Copyright 2008
+ * Graeme Russ, [email protected].
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <netdev.h>
+
+#ifdef CONFIG_HW_WATCHDOG
+#include <watchdog.h>
+#endif
+
+#include "hardware.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN;
+
+
+/*
+ * Miscellaneous platform dependent initializations
+ */
+int board_early_init_f(void)
+{
+
+ return 0;
+}
+
+
+
+int board_early_init_r(void)
+{
+ /* CPU Speed to 100MHz */
+ gd->cpu_clk = 100000000;
+
+ /* Crystal is 33.000MHz */
+ gd->bus_clk = 33000000;
+
+ return 0;
+}
+
+void show_boot_progress(int val)
+{
+}
+
+
+int last_stage_init(void)
+{
+ int minor;
+ int major;
+
+
+// register_timer_isr(enet_timer_isr);
+
+ printf("Serck Controls eNET\n");
+
+ return 0;
+}
+
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
+
+void setup_pcat_compatibility()
+{
+}
+
+
+void hw_watchdog_reset(void)
+{
+}
+
+void enet_toggle_run_led(void)
+{
+}
diff --git a/board/coreboot/coreboot_pci.c b/board/coreboot/coreboot_pci.c
new file mode 100644
index 0000000..87e90f4
--- /dev/null
+++ b/board/coreboot/coreboot_pci.c
@@ -0,0 +1,76 @@
+/*
+ * (C) Copyright 2008,2009
+ * Graeme Russ, <[email protected]>
+ *
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB, <[email protected]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/pci.h>
+#include <asm/ic/pci.h>
+
+static void pci_enet_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
+{
+}
+
+static struct pci_controller enet_hose = {
+ fixup_irq: pci_enet_fixup_irq,
+};
+
+void pci_init_board(void)
+{
+ pci_sc520_init(&enet_hose);
+}
+
+int pci_set_regions(struct pci_controller *hose)
+{
+ /* System memory space */
+ pci_set_region(hose->regions + 0,
+ SC520_PCI_MEMORY_BUS,
+ SC520_PCI_MEMORY_PHYS,
+ SC520_PCI_MEMORY_SIZE,
+ PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+
+ /* ISA/PCI memory space */
+ pci_set_region(hose->regions + 1,
+ SC520_ISA_MEM_BUS,
+ SC520_ISA_MEM_PHYS,
+ SC520_ISA_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* PCI I/O space */
+ pci_set_region(hose->regions + 2,
+ SC520_PCI_IO_BUS,
+ SC520_PCI_IO_PHYS,
+ SC520_PCI_IO_SIZE,
+ PCI_REGION_IO);
+
+ /* ISA/PCI I/O space */
+ pci_set_region(hose->regions + 3,
+ SC520_ISA_IO_BUS,
+ SC520_ISA_IO_PHYS,
+ SC520_ISA_IO_SIZE,
+ PCI_REGION_IO);
+
+ return 4;
+}
diff --git a/board/coreboot/coreboot_start.S b/board/coreboot/coreboot_start.S
new file mode 100644
index 0000000..0dec7ea
--- /dev/null
+++ b/board/coreboot/coreboot_start.S
@@ -0,0 +1,30 @@
+/*
+ * (C) Copyright 2008
+ * Graeme Russ, [email protected].
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include "hardware.h"
+
+/* board early intialization */
+.globl early_board_init
+early_board_init:
+ /* No 32-bit board specific initialisation */
+ jmp early_board_init_ret
diff --git a/board/coreboot/coreboot_start16.S b/board/coreboot/coreboot_start16.S
new file mode 100644
index 0000000..60fb842
--- /dev/null
+++ b/board/coreboot/coreboot_start16.S
@@ -0,0 +1,51 @@
+/*
+ * (C) Copyright 2008
+ * Graeme Russ, [email protected].
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * 16bit initialization code.
+ * This code have to map the area of the boot flash
+ * that is used by U-boot to its final destination.
+ */
+
+/* #include <asm/ic/sc520_defs.h> */
+
+#include "config.h"
+#include "hardware.h"
+#include <asm/ic/sc520.h>
+
+.text
+.section .start16, "ax"
+.code16
+.globl board_init16
+board_init16:
+ jmp board_init16_ret
+
+.section .bios, "ax"
+.code16
+.globl realmode_reset
+.hidden realmode_reset
+.type realmode_reset, @function
+realmode_reset:
+
+1: hlt
+ jmp 1
diff --git a/board/coreboot/hardware.h b/board/coreboot/hardware.h
new file mode 100644
index 0000000..38febfe
--- /dev/null
+++ b/board/coreboot/hardware.h
@@ -0,0 +1,28 @@
+/*
+ * (C) Copyright 2008
+ * Graeme Russ, [email protected].
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef HARDWARE_H_
+#define HARDWARE_H_
+
+
+#endif /* HARDWARE_H_ */
diff --git a/boards.cfg b/boards.cfg
index 554e06c..1523cb9 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -205,7 +205,8 @@ ibf-dsp561 blackfin blackfin
ip04 blackfin blackfin
tcm-bf518 blackfin blackfin
tcm-bf537 blackfin blackfin
-eNET x86 x86 eNET - sc520 eNET:SYS_TEXT_BASE=0x38040000
+coreboot x86 x86 coreboot - coreboot coreboot:SYS_TEXT_BASE=0xFC0000
+eNET x86 x86 eNET - coreboot eNET:SYS_TEXT_BASE=0xFC0000
eNET_SRAM x86 x86 eNET - sc520 eNET:SYS_TEXT_BASE=0x19000000
idmr m68k mcf52x2
TASREG m68k mcf52x2 tasreg esd
diff --git a/build b/build
new file mode 100644
index 0000000..2645cd2
--- /dev/null
+++ b/build
@@ -0,0 +1,3 @@
+make CROSS_COMPILE=i386-elf-
+nasm -f elf wrap.asm
+i386-elf-ld -Ttext=0xfC0000 wrap.o
diff --git a/common/serial.c b/common/serial.c
index 8ebf9a5..23d26ec 100644
--- a/common/serial.c
+++ b/common/serial.c
@@ -42,7 +42,7 @@ struct serial_device *__default_serial_console (void)
|| defined(CONFIG_MB86R0x) || defined(CONFIG_MPC5xxx) \
|| defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) \
|| defined(CONFIG_MPC86xx) || defined(CONFIG_SYS_SC520) \
- || defined(CONFIG_TEGRA2)
+ || defined(CONFIG_TEGRA2) || defined(CONFIG_SYS_COREBOOT)
#if defined(CONFIG_CONS_INDEX) && defined(CONFIG_SYS_NS16550_SERIAL)
#if (CONFIG_CONS_INDEX==1)
return &eserial1_device;
diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h
new file mode 100644
index 0000000..8946110
--- /dev/null
+++ b/include/configs/coreboot.h
@@ -0,0 +1,618 @@
+/*
+ * (C) Copyright 2008
+ * Graeme Russ, [email protected].
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/ibmpc.h>
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_SYS_COREBOOT
+#define CONFIG_SHOW_BOOT_PROGRESS
+#define CONFIG_LAST_STAGE_INIT
+
+
+/*-----------------------------------------------------------------------
+ * Watchdog Configuration
+ * NOTE: If CONFIG_HW_WATCHDOG is NOT defined, the watchdog jumper on the
+ * bottom (processor) board MUST be removed!
+ */
+#undef CONFIG_WATCHDOG
+#define CONFIG_HW_WATCHDOG
+
+/*-----------------------------------------------------------------------
+ * Real Time Clock Configuration
+ */
+#define CONFIG_RTC_MC146818
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0
+
+/*-----------------------------------------------------------------------
+ * Serial Configuration
+ */
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK 1843200
+#define CONFIG_BAUDRATE 9600
+#define CONFIG_SYS_BAUDRATE_TABLE {300, 600, 1200, 2400, 4800, \
+ 9600, 19200, 38400, 115200}
+#define CONFIG_SYS_NS16550_COM1 UART0_BASE
+#define CONFIG_SYS_NS16550_COM2 UART1_BASE
+#define CONFIG_SYS_NS16550_PORT_MAPPED
+
+/*-----------------------------------------------------------------------
+ * Video Configuration
+ */
+#undef CONFIG_VIDEO
+#undef CONFIG_CFB_CONSOLE
+
+/*-----------------------------------------------------------------------
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_BOOTD
+#define CONFIG_CMD_CONSOLE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_FPGA
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_IMLS
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_ITEST
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_SETGETDCR
+#define CONFIG_CMD_SOURCE
+#define CONFIG_CMD_XIMG
+
+#define CONFIG_BOOTDELAY 15
+#define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyS0,9600"
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 115200
+#define CONFIG_KGDB_SER_INDEX 2
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT "boot > "
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + \
+ 16)
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MEMTEST_START 0x00100000
+#define CONFIG_SYS_MEMTEST_END 0x01000000
+#define CONFIG_SYS_LOAD_ADDR 0x100000
+#define CONFIG_SYS_HZ 1000
+
+/*-----------------------------------------------------------------------
+ * SDRAM Configuration
+ */
+#define CONFIG_SYS_SDRAM_DRCTMCTL 0x18
+#define CONFIG_SYS_SDRAM_REFRESH_RATE 156
+#define CONFIG_NR_DRAM_BANKS 4
+
+/* CONFIG_SYS_SDRAM_DRCTMCTL Overrides the following*/
+#undef CONFIG_SYS_SDRAM_PRECHARGE_DELAY
+#undef CONFIG_SYS_SDRAM_RAS_CAS_DELAY
+#undef CONFIG_SYS_SDRAM_CAS_LATENCY_2T
+#undef CONFIG_SYS_SDRAM_CAS_LATENCY_3T
+
+/*-----------------------------------------------------------------------
+ * CPU Features
+ */
+
+#define CONFIG_SYS_GENERIC_TIMER
+#define CONFIG_SYS_PCAT_INTERRUPTS
+#define CONFIG_SYS_NUM_IRQS 16
+
+/*-----------------------------------------------------------------------
+ * Memory organization:
+ * 32kB Stack
+ * 16kB Cache-As-RAM @ 0x19200000
+ * 256kB Monitor
+ * (128kB + Environment Sector Size) malloc pool
+ */
+#define CONFIG_SYS_STACK_SIZE (32 * 1024)
+#define CONFIG_SYS_CAR_ADDR (256*1024)
+#define CONFIG_SYS_CAR_SIZE (16 * 1024)
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_CAR_ADDR + \
+ CONFIG_SYS_CAR_SIZE)
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SECT_SIZE + \
+ 128*1024)
+/* Address of temporary Global Data */
+#define CONFIG_SYS_INIT_GD_ADDR CONFIG_SYS_CAR_ADDR
+
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/*-----------------------------------------------------------------------
+ * FLASH configuration
+ * 512kB Boot Flash @ 0x38000000 (Monitor @ 38040000)
+ * 16MB StrataFlash #1 @ 0x10000000
+ * 16MB StrataFlash #2 @ 0x11000000
+ */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_LEGACY
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_MAX_FLASH_BANKS 3
+#define CONFIG_SYS_FLASH_BASE 0x38000000
+#define CONFIG_SYS_FLASH_BASE_1 0x10000000
+#define CONFIG_SYS_FLASH_BASE_2 0x11000000
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \
+ CONFIG_SYS_FLASH_BASE_1, \
+ CONFIG_SYS_FLASH_BASE_2}
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_MAX_FLASH_SECT 128
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
+#define CONFIG_SYS_FLASH_LEGACY_512Kx8
+#define CONFIG_SYS_FLASH_ERASE_TOUT 2000 /* ms */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 2000 /* ms */
+
+/*-----------------------------------------------------------------------
+ * Environment configuration
+ * - Boot flash is 512kB with 64kB sectors
+ * - StrataFlash is 32MB with 128kB sectors
+ * - Redundant embedded environment is 25% of the Boot flash
+ * - Redundant StrataFlash environment is <1% of the StrataFlash
+ * - Environment is therefore located in StrataFlash
+ * - Primary copy is located in first sector of first flash
+ * - Redundant copy is located in second sector of first flash
+ * - Stack is only 32kB, so environment size is limited to 4kB
+ */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE 0x20000
+#define CONFIG_ENV_SIZE 0x01000
+#define CONFIG_ENV_ADDR CONFIG_SYS_FLASH_BASE_1
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE_1 + \
+ CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+
+/*-----------------------------------------------------------------------
+ * PCI configuration
+ */
+#define CONFIG_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_SYS_FIRST_PCI_IRQ 10
+#define CONFIG_SYS_SECOND_PCI_IRQ 9
+#define CONFIG_SYS_THIRD_PCI_IRQ 11
+#define CONFIG_SYS_FORTH_PCI_IRQ 15
+
+/*-----------------------------------------------------------------------
+ * Network device (TRL8100B) support
+ */
+#define CONFIG_NET_MULTI
+#define CONFIG_RTL8139
+
+/*-----------------------------------------------------------------------
+ * BOOTCS Control (for AM29LV040B-120JC)
+ *
+ * 000 0 00 0 000 11 0 011 }- 0x0033
+ * \ / | \| | \ / \| | \ /
+ * | | | | | | | |
+ * | | | | | | | +---- 3 Wait States (First Access)
+ * | | | | | | +------- Reserved
+ * | | | | | +--------- 3 Wait States (Subsequent Access)
+ * | | | | +------------- Reserved
+ * | | | +---------------- Non-Paged Mode
+ * | | +------------------ 8 Bit Wide
+ * | +--------------------- GP Bus
+ * +------------------------ Reserved
+ */
+#define CONFIG_SYS_SC520_BOOTCS_CTRL 0x0033
+
+/*-----------------------------------------------------------------------
+ * ROMCS Control (for E28F128J3A-150 StrataFlash)
+ *
+ * 000 0 01 1 000 01 0 101 }- 0x0615
+ * \ / | \| | \ / \| | \ /
+ * | | | | | | | |
+ * | | | | | | | +---- 5 Wait States (First Access)
+ * | | | | | | +------- Reserved
+ * | | | | | +--------- 1 Wait State (Subsequent Access)
+ * | | | | +------------- Reserved
+ * | | | +---------------- Paged Mode
+ * | | +------------------ 16 Bit Wide
+ * | +--------------------- GP Bus
+ * +------------------------ Reserved
+ */
+#define CONFIG_SYS_SC520_ROMCS1_CTRL 0x0615
+#define CONFIG_SYS_SC520_ROMCS2_CTRL 0x0615
+
+/*-----------------------------------------------------------------------
+ * SC520 General Purpose Bus configuration
+ *
+ * Chip Select Offset 1 Clock Cycle
+ * Chip Select Pulse Width 8 Clock Cycles
+ * Chip Select Read Offset 2 Clock Cycles
+ * Chip Select Read Width 6 Clock Cycles
+ * Chip Select Write Offset 2 Clock Cycles
+ * Chip Select Write Width 6 Clock Cycles
+ * Chip Select Recovery Time 2 Clock Cycles
+ *
+ * Timing Diagram (from SC520 Register Set Manual - Order #22005B)
+ *
+ * |<-------------General Purpose Bus Cycle---------------->|
+ * | |
+ * ----------------------\__________________/------------------
+ * |<--(GPCSOFF + 1)-->|<--(GPCSPW + 1)-->|<-(GPCSRT + 1)-> |
+ *
+ * ------------------------\_______________/-------------------
+ * |<---(GPRDOFF + 1)--->|<-(GPRDW + 1)->|
+ *
+ * --------------------------\_______________/-----------------
+ * |<----(GPWROFF + 1)---->|<-(GPWRW + 1)->|
+ *
+ * ________/-----------\_______________________________________
+ * |<--->|<--------->|
+ * ^ ^
+ * (GPALEOFF + 1) |
+ * |
+ * (GPALEW + 1)
+ */
+#define CONFIG_SYS_SC520_GPCSOFF 0x00
+#define CONFIG_SYS_SC520_GPCSPW 0x07
+#define CONFIG_SYS_SC520_GPRDOFF 0x01
+#define CONFIG_SYS_SC520_GPRDW 0x05
+#define CONFIG_SYS_SC520_GPWROFF 0x01
+#define CONFIG_SYS_SC520_GPWRW 0x05
+#define CONFIG_SYS_SC520_GPCSRT 0x01
+
+/*-----------------------------------------------------------------------
+ * SC520 Programmable I/O configuration
+ *
+ * Pin Mode Dir. Description
+ * ----------------------------------------------------------------------
+ * PIO0 PIO Output Unused
+ * PIO1 GPBHE# Output GP Bus Byte High Enable (active low)
+ * PIO2 PIO Output Auxiliary power output enable
+ * PIO3 GPAEN Output GP Bus Address Enable
+ * PIO4 PIO Output Top Board Enable (active low)
+ * PIO5 PIO Output StrataFlash 16 bit mode (low = 8 bit mode)
+ * PIO6 PIO Input Data output of Power Supply ADC
+ * PIO7 PIO Output Clock input to Power Supply ADC
+ * PIO8 PIO Output Chip Select input of Power Supply ADC
+ * PIO9 PIO Output StrataFlash 1 Reset / Power Down (active low)
+ * PIO10 PIO Output StrataFlash 2 Reset / Power Down (active low)
+ * PIO11 PIO Input StrataFlash 1 Status
+ * PIO12 PIO Input StrataFlash 2 Status
+ * PIO13 GPIRQ10# Input Can Bus / I2C IRQ (active low)
+ * PIO14 PIO Input Low Input Voltage Warning (active low)
+ * PIO15 PIO Output Watchdog (must toggle at least every 1.6s)
+ * PIO16 PIO Input Power Fail
+ * PIO17 GPIRQ6 Input Compact Flash 1 IRQ (active low)
+ * PIO18 GPIRQ5 Input Compact Flash 2 IRQ (active low)
+ * PIO19 GPIRQ4# Input Dual-Port RAM IRQ (active low)
+ * PIO20 GPIRQ3 Input UART D IRQ
+ * PIO21 GPIRQ2 Input UART C IRQ
+ * PIO22 GPIRQ1 Input UART B IRQ
+ * PIO23 GPIRQ0 Input UART A IRQ
+ * PIO24 GPDBUFOE# Output GP Bus Data Bus Buffer Output Enable
+ * PIO25 PIO Input Battery OK Indication
+ * PIO26 GPMEMCS16# Input GP Bus Memory Chip-Select 16-bit access
+ * PIO27 GPCS0# Output SRAM 1 Chip Select
+ * PIO28 PIO Input Top Board UART CTS
+ * PIO29 PIO Output FPGA Program Mode (active low)
+ * PIO30 PIO Input FPGA Initialised (active low)
+ * PIO31 PIO Input FPGA Done (active low)
+ */
+#define CONFIG_SYS_SC520_PIOPFS15_0 0x200a
+#define CONFIG_SYS_SC520_PIOPFS31_16 0x0dfe
+#define CONFIG_SYS_SC520_PIODIR15_0 0x87bf
+#define CONFIG_SYS_SC520_PIODIR31_16 0x2900
+
+/*-----------------------------------------------------------------------
+ * PIO Pin defines
+ */
+#define CONFIG_SYS_ENET_AUX_PWR 0x0004
+#define CONFIG_SYS_ENET_TOP_BRD_PWR 0x0010
+#define CONFIG_SYS_ENET_SF_WIDTH 0x0020
+#define CONFIG_SYS_ENET_PWR_ADC_DATA 0x0040
+#define CONFIG_SYS_ENET_PWR_ADC_CLK 0x0080
+#define CONFIG_SYS_ENET_PWR_ADC_CS 0x0100
+#define CONFIG_SYS_ENET_SF1_MODE 0x0200
+#define CONFIG_SYS_ENET_SF2_MODE 0x0400
+#define CONFIG_SYS_ENET_SF1_STATUS 0x0800
+#define CONFIG_SYS_ENET_SF2_STATUS 0x1000
+#define CONFIG_SYS_ENET_PWR_STATUS 0x4000
+#define CONFIG_SYS_ENET_WATCHDOG 0x8000
+
+#define CONFIG_SYS_ENET_PWR_FAIL 0x0001
+#define CONFIG_SYS_ENET_BAT_OK 0x0200
+#define CONFIG_SYS_ENET_TOP_BRD_CTS 0x1000
+#define CONFIG_SYS_ENET_FPGA_PROG 0x2000
+#define CONFIG_SYS_ENET_FPGA_INIT 0x4000
+#define CONFIG_SYS_ENET_FPGA_DONE 0x8000
+
+/*-----------------------------------------------------------------------
+ * Chip Select Pin Function Select
+ *
+ * 1 1 1 1 1 0 0 0 }- 0xf8
+ * | | | | | | | |
+ * | | | | | | | +--- Reserved
+ * | | | | | | +----- GPCS1_SEL = ROMCS1#
+ * | | | | | +------- GPCS2_SEL = ROMCS2#
+ * | | | | +--------- GPCS3_SEL = GPCS3
+ * | | | +----------- GPCS4_SEL = GPCS4
+ * | | +------------- GPCS5_SEL = GPCS5
+ * | +--------------- GPCS6_SEL = GPCS6
+ * +----------------- GPCS7_SEL = GPCS7
+ */
+#define CONFIG_SYS_SC520_CSPFS 0xf8
+
+/*-----------------------------------------------------------------------
+ * Clock Select (CLKTIMER[CLKTEST] pin)
+ *
+ * 0 111 00 1 0 }- 0x72
+ * | \ / \| | |
+ * | | | | +--- Pin Disabled
+ * | | | +----- Pin is an output
+ * | | +------- Reserved
+ * | +----------- Disabled (pin stays Low)
+ * +-------------- Reserved
+ */
+#define CONFIG_SYS_SC520_CLKSEL 0x72
+
+/*-----------------------------------------------------------------------
+ * Address Decode Control
+ *
+ * 0 00 0 0 0 0 0 }- 0x00
+ * | \| | | | | |
+ * | | | | | | +--- Integrated UART 1 is enabled
+ * | | | | | +----- Integrated UART 2 is enabled
+ * | | | | +------- Integrated RTC is enabled
+ * | | | +--------- Reserved
+ * | | +----------- I/O Hole accesses are forwarded to the external GP bus
+ * | +------------- Reserved
+ * +---------------- Write-protect violations do not generate an IRQ
+ */
+#define CONFIG_SYS_SC520_ADDDECCTL 0x00
+
+/*-----------------------------------------------------------------------
+ * UART Control
+ *
+ * 00000 1 1 1 }- 0x07
+ * \___/ | | |
+ * | | | +--- Transmit TC interrupt enable
+ * | | +----- Receive TC interrupt enable
+ * | +------- 1.8432 MHz
+ * +----------- Reserved
+ */
+#define CONFIG_SYS_SC520_UART1CTL 0x07
+#define CONFIG_SYS_SC520_UART2CTL 0x07
+
+/*-----------------------------------------------------------------------
+ * System Arbiter Control
+ *
+ * 00000 1 1 0 }- 0x06
+ * \___/ | | |
+ * | | | +--- Disable PCI Bus Arbiter Grant Time-Out Interrupt
+ * | | +----- The system arbiter operates in concurrent mode
+ * | +------- Park the PCI bus on the last master that acquired the bus
+ * +----------- Reserved
+ */
+#define CONFIG_SYS_SC520_SYSARBCTL 0x06
+
+/*-----------------------------------------------------------------------
+ * System Arbiter Master Enable
+ *
+ * 00000000000 0 0 0 1 1 }- 0x06
+ * \_________/ | | | | |
+ * | | | | | +--- PCI master REQ0 enabled (Ethernet 1)
+ * | | | | +----- PCI master REQ1 enabled (Ethernet 2)
+ * | | | +------- PCI master REQ2 disabled
+ * | | +--------- PCI master REQ3 disabled
+ * | +----------- PCI master REQ4 disabled
+ * +------------------ Reserved
+ */
+#define CONFIG_SYS_SC520_SYSARBMENB 0x0003
+
+/*-----------------------------------------------------------------------
+ * System Arbiter Master Enable
+ *
+ * 0 0000 0 00 0000 1 000 }- 0x06
+ * | \__/ | \| \__/ | \_/
+ * | | | | | | +---- Reserved
+ * | | | | | +------- Enable CPU-to-PCI bus write posting
+ * | | | | +---------- Reserved
+ * | | | +-------------- PCI bus reads to SDRAM are not automatically
+ * | | | retried
+ * | | +----------------- Target read FIFOs are not snooped during write
+ * | | transactions
+ * | +-------------------- Reserved
+ * +------------------------ Deassert the PCI bus reset signal
+ */
+#define CONFIG_SYS_SC520_HBCTL 0x08
+
+/*-----------------------------------------------------------------------
+ * PAR for Boot Flash - 512kB @ 0x38000000, BOOTCS
+ * 100 0 1 0 1 00000000111 11100000000000 }- 0x8a01f800
+ * \ / | | | | \----+----/ \-----+------/
+ * | | | | | | +---------- Start at 0x38000000
+ * | | | | | +----------------------- 512kB Region Size
+ * | | | | | ((7 + 1) * 64kB)
+ * | | | | +------------------------------ 64kB Page Size
+ * | | | +-------------------------------- Writes Enabled (So it can be
+ * | | | reprogrammed!)
+ * | | +---------------------------------- Caching Disabled
+ * | +------------------------------------ Execution Enabled
+ * +--------------------------------------- BOOTCS
+ */
+#define CONFIG_SYS_SC520_BOOTCS_PAR 0x8a01f800
+
+/*-----------------------------------------------------------------------
+ * Cache-As-RAM (Targets Boot Flash)
+ *
+ * 100 1 0 0 0 0001111 011001001000000000 }- 0x903d9200
+ * \ / | | | | \--+--/ \-------+--------/
+ * | | | | | | +------------ Start at 0x19200000
+ * | | | | | +------------------------- 64k Region Size
+ * | | | | | ((15 + 1) * 4kB)
+ * | | | | +------------------------------ 4kB Page Size
+ * | | | +-------------------------------- Writes Enabled
+ * | | +---------------------------------- Caching Enabled
+ * | +------------------------------------ Execution Prevented
+ * +--------------------------------------- BOOTCS
+ */
+#define CONFIG_SYS_SC520_CAR_PAR 0x903d9200
+
+/*-----------------------------------------------------------------------
+ * PAR for Low Level I/O (LEDs, Hex Switches etc) - 33 Bytes @ 0x1000, GPCS6
+ *
+ * 001 110 0 000100000 0001000000000000 }- 0x38201000
+ * \ / \ / | \---+---/ \------+-------/
+ * | | | | +----------- Start at 0x00001000
+ * | | | +------------------------ 33 Bytes (0x20 + 1)
+ * | | +------------------------------ Ignored
+ * | +--------------------------------- GPCS6
+ * +------------------------------------- GP Bus I/O
+ */
+#define CONFIG_SYS_SC520_LLIO_PAR 0x38201000
+
+/*-----------------------------------------------------------------------
+ * PAR for Compact Flash Port #1 - 4kB @ 0x200000000, CS5
+ * PAR for Compact Flash Port #2 - 4kB @ 0x200010000, CS7
+ *
+ * 010 101 0 0000000 100000000000000000 }- 0x54020000
+ * 010 111 0 0000000 100000000000000001 }- 0x5c020001
+ * \ / \ / | \--+--/ \-------+--------/
+ * | | | | +------------ Start at 0x200000000
+ * | | | | 0x200010000
+ * | | | +------------------------- 4kB Region Size
+ * | | | ((0 + 1) * 4kB)
+ * | | +------------------------------ 4k Page Size
+ * | +--------------------------------- GPCS5
+ * | GPCS7
+ * +------------------------------------- GP Bus Memory
+ */
+#define CONFIG_SYS_SC520_CF1_PAR 0x54020000
+#define CONFIG_SYS_SC520_CF2_PAR 0x5c020001
+
+/*-----------------------------------------------------------------------
+ * PAR for Extra 16550 UART A - 8 bytes @ 0x013f8, GPCS0
+ * PAR for Extra 16550 UART B - 8 bytes @ 0x012f8, GPCS3
+ * PAR for Extra 16550 UART C - 8 bytes @ 0x011f8, GPCS4
+ * PAR for Extra 16550 UART D - 8 bytes @ 0x010f8, GPCS5
+ *
+ * 001 000 0 000000111 0001001111111000 }- 0x200713f8
+ * 001 011 0 000000111 0001001011111000 }- 0x2c0712f8
+ * 001 011 0 000000111 0001001011111000 }- 0x300711f8
+ * 001 011 0 000000111 0001001011111000 }- 0x340710f8
+ * \ / \ / | \---+---/ \------+-------/
+ * | | | | +----------- Start at 0x013f8
+ * | | | | 0x012f8
+ * | | | | 0x011f8
+ * | | | | 0x010f8
+ * | | | +------------------------ 33 Bytes (32 + 1)
+ * | | +------------------------------ Ignored
+ * | +--------------------------------- GPCS6
+ * +------------------------------------- GP Bus I/O
+ */
+#define CONFIG_SYS_SC520_UARTA_PAR 0x200713f8
+#define CONFIG_SYS_SC520_UARTB_PAR 0x2c0712f8
+#define CONFIG_SYS_SC520_UARTC_PAR 0x300711f8
+#define CONFIG_SYS_SC520_UARTD_PAR 0x340710f8
+
+/*-----------------------------------------------------------------------
+ * PAR for StrataFlash #1 - 16MB @ 0x10000000, ROMCS1
+ * PAR for StrataFlash #2 - 16MB @ 0x11000000, ROMCS2
+ *
+ * 101 0 1 0 1 00011111111 01000000000000 }- 0xaa3fd000
+ * 110 0 1 0 1 00011111111 01000100000000 }- 0xca3fd100
+ * \ / | | | | \----+----/ \-----+------/
+ * | | | | | | +---------- Start at 0x10000000
+ * | | | | | | 0x11000000
+ * | | | | | +----------------------- 16MB Region Size
+ * | | | | | ((255 + 1) * 64kB)
+ * | | | | +------------------------------ 64kB Page Size
+ * | | | +-------------------------------- Writes Enabled
+ * | | +---------------------------------- Caching Disabled
+ * | +------------------------------------ Execution Enabled
+ * +--------------------------------------- ROMCS1
+ * ROMCS2
+ */
+#define CONFIG_SYS_SC520_SF1_PAR 0xaa3fd000
+#define CONFIG_SYS_SC520_SF2_PAR 0xca3fd100
+
+/*-----------------------------------------------------------------------
+ * PAR for SRAM #1 - 1MB @ 0x19000000, GPCS0
+ * PAR for SRAM #2 - 1MB @ 0x19100000, GPCS3
+ *
+ * 010 000 1 00000001111 01100100000000 }- 0x4203d900
+ * 010 011 1 00000001111 01100100010000 }- 0x4e03d910
+ * \ / \ / | \----+----/ \-----+------/
+ * | | | | +---------- Start at 0x19000000
+ * | | | | 0x19100000
+ * | | | +----------------------- 1MB Region Size
+ * | | | ((15 + 1) * 64kB)
+ * | | +------------------------------ 64kB Page Size
+ * | +--------------------------------- GPCS0
+ * | GPCS3
+ * +------------------------------------- GP Bus Memory
+ */
+#define CONFIG_SYS_SC520_SRAM1_PAR 0x4203d900
+#define CONFIG_SYS_SC520_SRAM2_PAR 0x4e03d910
+
+/*-----------------------------------------------------------------------
+ * PAR for Dual-Port RAM - 4kB @ 0x18100000, GPCS4
+ *
+ * 010 100 0 00000000 11000000100000000 }- 0x50018100
+ * \ / \ / | \---+--/ \-------+-------/
+ * | | | | +----------- Start at 0x18100000
+ * | | | +------------------------ 4kB Region Size
+ * | | | ((0 + 1) * 4kB)
+ * | | +------------------------------ 4kB Page Size
+ * | +--------------------------------- GPCS4
+ * +------------------------------------- GP Bus Memory
+ */
+#define CONFIG_SYS_SC520_DPRAM_PAR 0x50018100
+
+#endif /* __CONFIG_H */
diff --git a/include/serial.h b/include/serial.h
index f21d961..318cbdb 100644
--- a/include/serial.h
+++ b/include/serial.h
@@ -28,7 +28,7 @@ extern struct serial_device * default_serial_console (void);
defined(CONFIG_MB86R0x) || defined(CONFIG_MPC5xxx) || \
defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || \
defined(CONFIG_MPC86xx) || defined(CONFIG_SYS_SC520) || \
- defined(CONFIG_TEGRA2)
+ defined(CONFIG_TEGRA2) || defined(CONFIG_SYS_COREBOOT)
extern struct serial_device serial0_device;
extern struct serial_device serial1_device;
#if defined(CONFIG_SYS_NS16550_SERIAL)
diff --git a/wrap.asm b/wrap.asm
new file mode 100644
index 0000000..f03cccd
--- /dev/null
+++ b/wrap.asm
@@ -0,0 +1,4 @@
+section .text
+global _start
+_start:
+incbin "u-boot.bin"
--
1.7.1
>From 24b6bc23ade67fa80562222f6b214c1f3709e634 Mon Sep 17 00:00:00 2001
From: Rudolf Marek <ruik@ruik.(none)>
Date: Sat, 30 Apr 2011 22:33:48 +0200
Subject: [PATCH 2/2] Fixes2
---
arch/x86/lib/bios_setup.c | 2 +-
arch/x86/lib/realmode.c | 6 +++++-
include/configs/coreboot.h | 29 +++++++++++++++++++++++++++++
3 files changed, 35 insertions(+), 2 deletions(-)
diff --git a/arch/x86/lib/bios_setup.c b/arch/x86/lib/bios_setup.c
index 6949b35..4488ce6 100644
--- a/arch/x86/lib/bios_setup.c
+++ b/arch/x86/lib/bios_setup.c
@@ -140,7 +140,7 @@ static void setvector(int vector, u16 segment, void *handler)
int bios_setup(void)
{
- ulong bios_start = (ulong)&__bios_start + gd->reloc_off;
+ ulong bios_start = (ulong)&__bios_start - gd->reloc_off;
ulong bios_size = (ulong)&__bios_size;
static int done=0;
diff --git a/arch/x86/lib/realmode.c b/arch/x86/lib/realmode.c
index e518188..d396742 100644
--- a/arch/x86/lib/realmode.c
+++ b/arch/x86/lib/realmode.c
@@ -34,7 +34,7 @@ extern char realmode_enter;
int realmode_setup(void)
{
- ulong realmode_start = (ulong)&__realmode_start + gd->reloc_off;
+ ulong realmode_start = (ulong)&__realmode_start - gd->reloc_off;
ulong realmode_size = (ulong)&__realmode_size;
/* copy the realmode switch code */
@@ -42,7 +42,11 @@ int realmode_setup(void)
return -1;
}
+ printf("copy to %x from %x size %x \n", REALMODE_BASE, realmode_start, realmode_size);
+
memcpy((char *)REALMODE_BASE, (void *)realmode_start, realmode_size);
+
+ printf("copied %x\n" , (*(int *)REALMODE_BASE));
asm("wbinvd\n");
return 0;
diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h
index 8946110..1effe86 100644
--- a/include/configs/coreboot.h
+++ b/include/configs/coreboot.h
@@ -68,6 +68,31 @@
#define CONFIG_SYS_NS16550_COM2 UART1_BASE
#define CONFIG_SYS_NS16550_PORT_MAPPED
+
+#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 2 IDE busses */
+#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 2 drives per IDE bus */
+
+#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO_BASE_ADDRESS /* base address */
+#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
+#define CONFIG_SYS_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */
+#define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */
+#define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */
+#define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */
+
+
+#define CONFIG_SUPPORT_VFAT
+/************************************************************
+ * ATAPI support (experimental)
+ ************************************************************/
+#define CONFIG_ATAPI /* enable ATAPI Support */
+
+/************************************************************
+ * DISK Partition support
+ ************************************************************/
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MAC_PARTITION
+#define CONFIG_ISO_PARTITION /* Experimental */
+
/*-----------------------------------------------------------------------
* Video Configuration
*/
@@ -104,6 +129,10 @@
#define CONFIG_CMD_SOURCE
#define CONFIG_CMD_XIMG
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+
#define CONFIG_BOOTDELAY 15
#define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyS0,9600"
--
1.7.1
--
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