Hi Stefan, hi Eric, Stefan Reinauer <[email protected]> writes:
> * Eric W. Biederman <[email protected]> [110503 01:26]: >> Was that a destination hard code? The code itself should come out of >> the last couple of megabytes before 4G. > > Yes. Only the lower 1MB of the destination memory was cached, while > coreboot's ram stage is now copied to 1MB. thanks for all your help. I've did both changes (enabling SPI prefetch and setting the MTRRs right). Boot time decreased now to 1.8s (with only 1s spent in coreboot). Decompression time is now about 100ms, which is much better than what we had before (1.9s only for ramstage loading). Thanks, Sven. -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
