Author: mjones Date: Sun May 15 23:51:31 2011 New Revision: 6583 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6583
Log: Switch processor cores to pstate 0 early to reduce boot time. Signed-off-by: Scott Duplichan <[email protected]> Acked-by: Marc Jones <[email protected]> Modified: trunk/src/mainboard/amd/persimmon/romstage.c Modified: trunk/src/mainboard/amd/persimmon/romstage.c ============================================================================== --- trunk/src/mainboard/amd/persimmon/romstage.c Sun May 15 23:48:22 2011 (r6582) +++ trunk/src/mainboard/amd/persimmon/romstage.c Sun May 15 23:51:31 2011 (r6583) @@ -47,6 +47,9 @@ u32 val; u8 reg8; + // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time + __writemsr (0xc0010062, 0); + // early enable of SPI 33 MHz fast mode read if (boot_cpu()) { -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
