Author: mjones Date: Mon May 16 00:06:09 2011 New Revision: 6591 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6591
Log: Enable rom cache early to reduce boot time. Signed-off-by: Scott Duplichan <[email protected]> Acked-by: Marc Jones <[email protected]> Modified: trunk/src/mainboard/amd/persimmon/agesawrapper.c trunk/src/mainboard/amd/persimmon/romstage.c Modified: trunk/src/mainboard/amd/persimmon/agesawrapper.c ============================================================================== --- trunk/src/mainboard/amd/persimmon/agesawrapper.c Mon May 16 00:05:00 2011 (r6590) +++ trunk/src/mainboard/amd/persimmon/agesawrapper.c Mon May 16 00:06:09 2011 (r6591) @@ -157,13 +157,6 @@ PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5; - LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = (0x1000000000 - CONFIG_ROM_SIZE) | 0x800; - LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); - Status = AGESA_SUCCESS; return (UINT32)Status; } Modified: trunk/src/mainboard/amd/persimmon/romstage.c ============================================================================== --- trunk/src/mainboard/amd/persimmon/romstage.c Mon May 16 00:05:00 2011 (r6590) +++ trunk/src/mainboard/amd/persimmon/romstage.c Mon May 16 00:06:09 2011 (r6591) @@ -47,6 +47,11 @@ u32 val; u8 reg8; + // all cores: allow caching of flash chip code and data + // (there are no cache-as-ram reliability concerns with family 14h) + __writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5); + __writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800); + // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time __writemsr (0xc0010062, 0); -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
