On Sun, May 15, 2011 at 5:57 PM, Peter Stuge <[email protected]> wrote:
> repository service wrote:
>> +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c Mon May 16
>> 00:07:56 2011 (r6592)
> ..
>> @@ -414,15 +413,16 @@
>> break;
>>
>> case (0x15 << 3) | 0: /* 0:15:0 PCIe PortA */
>> + sb_config->PORTCONFIG[0].PortCfg.PortPresent = dev->enabled;
>> + return;
>> case (0x15 << 3) | 1: /* 0:15:1 PCIe PortB */
>> + sb_config->PORTCONFIG[1].PortCfg.PortPresent = dev->enabled;
>> + return;
>> case (0x15 << 3) | 2: /* 0:15:2 PCIe PortC */
>> + sb_config->PORTCONFIG[2].PortCfg.PortPresent = dev->enabled;
>> + return;
>
> coreboot uses tab indent, right?
>
> That said, this reading of devicetree is a great improvement!
Thanks for the tab fix.
>
>
>> case (0x15 << 3) | 3: /* 0:15:3 PCIe PortD */
>> - gpp_port = (dev->path.pci.devfn) & 0x03;
>> - if (dev->enabled) {
>> - sb_config->PORTCONFIG[gpp_port].PortCfg.PortPresent =
>> ENABLED;
>> - } else {
>> - sb_config->PORTCONFIG[gpp_port].PortCfg.PortPresent =
>> DISABLED;
>> - }
>> + sb_config->PORTCONFIG[3].PortCfg.PortPresent = dev->enabled;
>
> Is it guaranteed that ENABLED == dev->enabled and DISABLED == !dev-enabled?
>
>
Yes, it is an enable bit in the register and POR defaults to disabled.
--
http://se-eng.com
--
coreboot mailing list: [email protected]
http://www.coreboot.org/mailman/listinfo/coreboot
