On Sun, May 15, 2011 at 6:52 PM, Peter Stuge <[email protected]> wrote: > repository service wrote: >> Log: >> Enable SPI cacheline prefetch early to reduce boot time. > > This is the same commit message as the previous commit, r6584. > > .. > >> +++ trunk/src/mainboard/amd/persimmon/romstage.c Sun May 15 23:56:03 >> 2011 (r6585) >> @@ -50,6 +50,21 @@ >> // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time >> __writemsr (0xc0010062, 0); >> >> + if (boot_cpu()) >> + { >> + u8 reg8; >> + // SB800: program AcpiMmioEn to enable MMIO access to MiscCntrl register >> + outb(0x24, 0xCD6); >> + reg8 = inb(0xCD7); >> + reg8 |= 1; >> + reg8 &= ~(1 << 1); >> + outb(reg8, 0xCD7); >> + >> + // program SB800 MiscCntrl >> + *(volatile u32 *)(0xFED80000+0xE00+0x40) &= ~((1 << 0) | (1 << 2)); /* >> 48Mhz */ >> + *(volatile u32 *)(0xFED80000+0xE00+0x40) |= 1 << 1; /* 48Mhz */ >> + } > > ..but the code does something else? >
Ugh, Sorry, I put the wrong commit message. It should be the following. > Move SB800 clock init earlier to fix problem where initial serial port > output is garbled. > > Signed-off-by: Scott Duplichan <[email protected]> Does anyone have a recommendation to update,fix, or otherwise improve the svn history? Thanks, Marc -- http://se-eng.com -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
