Author: mjones Date: Fri Jun 3 21:59:52 2011 New Revision: 6619 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6619
Log: This patch sets max freq defaults for ddr2 and ddr3for fam10. Signed-off-by: Marc Jones <[email protected]> Acked-by: Scott Duplichan <[email protected]> Modified: trunk/src/northbridge/amd/amdmct/mct/mct.h trunk/src/northbridge/amd/amdmct/mct/mct_d.h trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h trunk/src/northbridge/amd/amdmct/wrappers/mcti.h trunk/src/northbridge/amd/amdmct/wrappers/mcti_d.c Modified: trunk/src/northbridge/amd/amdmct/mct/mct.h ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct/mct.h Fri Jun 3 21:46:25 2011 (r6618) +++ trunk/src/northbridge/amd/amdmct/mct/mct.h Fri Jun 3 21:59:52 2011 (r6619) @@ -496,18 +496,6 @@ 0=disable 1=enable*/ -#ifndef MAX_NODES_SUPPORTED -#define MAX_NODES_SUPPORTED 8 -#endif - -#ifndef MAX_DIMMS_SUPPORTED -#define MAX_DIMMS_SUPPORTED 8 -#endif - -#ifndef MAX_CS_SUPPORTED -#define MAX_CS_SUPPORTED 8 -#endif - /* global function */ u32 NodePresent(u32 Node); Modified: trunk/src/northbridge/amd/amdmct/mct/mct_d.h ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct/mct_d.h Fri Jun 3 21:46:25 2011 (r6618) +++ trunk/src/northbridge/amd/amdmct/mct/mct_d.h Fri Jun 3 21:59:52 2011 (r6619) @@ -667,23 +667,6 @@ yy1b = enable with DctSelIntLvAddr set to yyb */ -#ifndef MAX_NODES_SUPPORTED -#define MAX_NODES_SUPPORTED 8 -#endif - -#ifndef MAX_DIMMS_SUPPORTED -#define MAX_DIMMS_SUPPORTED 8 -#endif - -#ifndef MAX_CS_SUPPORTED -#define MAX_CS_SUPPORTED 8 -#endif - -#ifndef MCT_DIMM_SPARE_NO_WARM -#define MCT_DIMM_SPARE_NO_WARM 0 -#endif - - u32 Get_NB32(u32 dev, u32 reg); void Set_NB32(u32 dev, u32 reg, u32 val); u32 Get_NB32_index(u32 dev, u32 index_reg, u32 index); Modified: trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c Fri Jun 3 21:46:25 2011 (r6618) +++ trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c Fri Jun 3 21:59:52 2011 (r6619) @@ -1315,7 +1315,7 @@ u16 word; /* Get CPU Si Revision defined limit (NPT) */ - proposedFreq = 533; /* Rev F0 programmable max memclock is */ + proposedFreq = 800; /* Rev F0 programmable max memclock is */ /*Get User defined limit if "limit" mode */ if ( mctGet_NVbits(NV_MCTUSRTMGMODE) == 1) { Modified: trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h Fri Jun 3 21:46:25 2011 (r6618) +++ trunk/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h Fri Jun 3 21:59:52 2011 (r6619) @@ -728,22 +728,6 @@ yy1b = enable with DctSelIntLvAddr set to yyb */ -#ifndef MAX_NODES_SUPPORTED -#define MAX_NODES_SUPPORTED 8 -#endif - -#ifndef MAX_DIMMS_SUPPORTED -#define MAX_DIMMS_SUPPORTED 8 -#endif - -#ifndef MAX_CS_SUPPORTED -#define MAX_CS_SUPPORTED 8 -#endif - -#ifndef MCT_DIMM_SPARE_NO_WARM -#define MCT_DIMM_SPARE_NO_WARM 0 -#endif - u32 Get_NB32(u32 dev, u32 reg); void Set_NB32(u32 dev, u32 reg, u32 val); u32 Get_NB32_index(u32 dev, u32 index_reg, u32 index); Modified: trunk/src/northbridge/amd/amdmct/wrappers/mcti.h ============================================================================== --- trunk/src/northbridge/amd/amdmct/wrappers/mcti.h Fri Jun 3 21:46:25 2011 (r6618) +++ trunk/src/northbridge/amd/amdmct/wrappers/mcti.h Fri Jun 3 21:59:52 2011 (r6619) @@ -57,6 +57,18 @@ #define MAX_CS_SUPPORTED 8 #endif +#ifndef MCT_DIMM_SPARE_NO_WARM +#define MCT_DIMM_SPARE_NO_WARM 0 +#endif + +#ifndef MEM_MAX_LOAD_FREQ +#if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */ + #define MEM_MAX_LOAD_FREQ 800 +#else + #define MEM_MAX_LOAD_FREQ 400 +#endif +#endif + #define MCT_TRNG_KEEPOUT_START 0x00000C00 #define MCT_TRNG_KEEPOUT_END 0x00000CFF Modified: trunk/src/northbridge/amd/amdmct/wrappers/mcti_d.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/wrappers/mcti_d.c Fri Jun 3 21:46:25 2011 (r6618) +++ trunk/src/northbridge/amd/amdmct/wrappers/mcti_d.c Fri Jun 3 21:59:52 2011 (r6619) @@ -48,7 +48,7 @@ //val = 200; /* 200MHz(DDR400) */ //val = 266; /* 266MHz(DDR533) */ //val = 333; /* 333MHz(DDR667) */ - val = 400; /* 400MHz(DDR800) */ + val = MEM_MAX_LOAD_FREQ;; /* 400MHz(DDR800) */ break; case NV_ECC_CAP: #if SYSTEM_TYPE == SERVER @@ -237,7 +237,7 @@ static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat) { - pDCTstat->PresetmaxFreq = 400; + pDCTstat->PresetmaxFreq = MEM_MAX_LOAD_FREQ; } #ifdef UNUSED_CODE -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
