asrock e350m1: configure sb800 gpp ports to support onboard pcie nic.
sb800 cimx wrapper: Run the complete sb800 cimx sbBeforePciInit() function
once, after determining device 0x15 function enables.

Signed-off-by: Scott Duplichan <scott@notabs.org>


diff -d -u -r coreboot-c045b4c\src\mainboard\asrock\e350m1\devicetree.cb coreboot-pcie-fix\src\mainboard\asrock\e350m1\devicetree.cb
--- coreboot-c045b4c\src\mainboard\asrock\e350m1\devicetree.cb	Thu Jun 16 10:20:56 2011
+++ coreboot-pcie-fix\src\mainboard\asrock\e350m1\devicetree.cb	Fri Jun 17 21:11:52 2011
@@ -99,11 +99,19 @@
 					end #LPC
   					device pci 14.4 on end # PCI 0x4384
 	  				device pci 14.5 on end # USB 2
-					device pci 15.0 off end # PCIe PortA
-					device pci 15.1 off end # PCIe PortB
+					device pci 15.0 on  end # PCIe PortA
+					device pci 15.1 on  end # PCIe PortB
 					device pci 15.2 off end # PCIe PortC
 					device pci 15.3 off end # PCIe PortD
-					register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow)
+
+					# gpp_configuration options
+					#0000: PortA lanes[3:0]
+					#0001: N/A
+					#0010: PortA lanes[1:0], PortB lanes[3:2]
+					#0011: PortA lanes[1:0], PortB lane2, PortC lane3
+					#0100: PortA lane0, PortB lane1, PortC lane2, PortD lane3.
+					register "gpp_configuration" = "4"
+
  		  			register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
 				end	#southbridge/amd/cimx_wrapper/sb800
 #                       end #  device pci 18.0
diff -d -u -r coreboot-c045b4c\src\southbridge\amd\cimx_wrapper\sb800\late.c coreboot-pcie-fix\src\southbridge\amd\cimx_wrapper\sb800\late.c
--- coreboot-c045b4c\src\southbridge\amd\cimx_wrapper\sb800\late.c	Thu Jun 16 10:20:56 2011
+++ coreboot-pcie-fix\src\southbridge\amd\cimx_wrapper\sb800\late.c	Fri Jun 17 21:16:51 2011
@@ -413,16 +413,13 @@
 		break;
 
 	case (0x15 << 3) | 0: /* 0:15:0 PCIe PortA */
-		sb_config->PORTCONFIG[0].PortCfg.PortPresent = dev->enabled;
-		return;
-	case (0x15 << 3) | 1: /* 0:15:1 PCIe PortB */
-		sb_config->PORTCONFIG[1].PortCfg.PortPresent = dev->enabled;
-		return;
-	case (0x15 << 3) | 2: /* 0:15:2 PCIe PortC */
-		sb_config->PORTCONFIG[2].PortCfg.PortPresent = dev->enabled;
-		return;
-	case (0x15 << 3) | 3: /* 0:15:3 PCIe PortD */
-		sb_config->PORTCONFIG[3].PortCfg.PortPresent = dev->enabled;
+		{
+		device_t device;
+		for (device = dev; device; device = device->next) {
+			if (dev->path.type != DEVICE_PATH_PCI) continue;
+			if ((device->path.pci.devfn & ~7) != PCI_DEVFN(0x15,0)) break;
+			sb_config->PORTCONFIG[device->path.pci.devfn & 3].PortCfg.PortPresent = device->enabled;
+		}
 
 		/*
 		 * GPP_CFGMODE_X4000: PortA Lanes[3:0]
@@ -430,22 +427,16 @@
 		 * GPP_CFGMODE_X2110: PortA Lanes[1:0], PortB Lane2, PortC Lane3
 		 * GPP_CFGMODE_X1111: PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3
 		 */
-		if (sb_config->GppLinkConfig != sb_chip->gpp_configuration) {
-			sb_config->GppLinkConfig = sb_chip->gpp_configuration;
-		}
-
-		sbPcieGppEarlyInit(sb_config);
+		sb_config->GppLinkConfig = sb_chip->gpp_configuration;
+		sb_config->StdHeader.Func = SB_BEFORE_PCI_INIT;
+		AmdSbDispatcher(sb_config);
 		break;
+		}
 
 	default:
 		break;
 	}
 
-	/* Special setting ABCFG registers before PCI emulation. */
-	abSpecialSetBeforePciEnum(sb_config);
-  	usbDesertPll(sb_config);
-	//sb_config->StdHeader.Func = SB_BEFORE_PCI_INIT;
-	//AmdSbDispatcher(sb_config);
 }
 
 struct chip_operations southbridge_amd_cimx_wrapper_sb800_ops = {