On 7/7/11 11:35 AM, Andrew Goodbody wrote: > Also I would expect that #4 NC is not NC at all, it just > does not go to the SPI device. It could very well be some way to allow > safe programming of the onboard SPI device such as by putting the board > into reset. I doubt that. There is no Pin which could lead anywhere ;)
I looked into the NM10 datasheet, which at least indicates, that CS# is input and output. And it seems that the chipset detects if some other SPI master pulls CS# to low. NM10 Express datasheet, page 58: >> SPI Chip Select: This chip select signal is also used as the SPI bus >> request signal. If that is the case, this pin is open-drain with an external pull-up. But I don't know what the board does, when it detects this condition. Perhaps it switches MISO, MOSI and SCK into a Z-State. Also, there is the SPI_ARB pin on the chipset. According to the datasheet it is used for the "shared flash" feature. I couldn't find any information about "shared flash", but I think this pin is used by a jumper to start a recovery mode on the board to reflash the BIOS in case of a previous failure. I connected my Bus Pirate yesterday, but I didn't get any data out of the flash. I'm just on a way to some place where I have an oscilloscope and logic analyzer to have some more fun :) - Andreas -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
