Move the AMD SB800 early clock setup code that is needed for early
serial port operation from mainboard/romstage.c to sb800/bootblock.c.
This prevents code duplication and simplifies porting.

Signed-off-by: Scott Duplichan <scott@notabs.org>


diff -u -r coreboot-1fe6c64\src\mainboard\amd\persimmon\romstage.c coreboot-update\src\mainboard\amd\persimmon\romstage.c
--- coreboot-1fe6c64\src\mainboard\amd\persimmon\romstage.c	Fri Jul 08 18:51:42 2011
+++ coreboot-update\src\mainboard\amd\persimmon\romstage.c	Sun Jul 10 00:24:51 2011
@@ -55,21 +55,6 @@
   // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
   __writemsr (0xc0010062, 0);
 
-  if (boot_cpu())
-    {
-    u8 reg8;
-    // SB800: program AcpiMmioEn to enable MMIO access to MiscCntrl register
-    outb(0x24, 0xCD6);
-    reg8 = inb(0xCD7);
-    reg8 |= 1;
-    reg8 &= ~(1 << 1);
-    outb(reg8, 0xCD7);
-  
-    // program SB800 MiscCntrl
-    *(volatile u32 *)(0xFED80000+0xE00+0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */
-    *(volatile u32 *)(0xFED80000+0xE00+0x40) |= 1 << 1; /* 48Mhz */
-    }
-
   if (!cpu_init_detectedx && boot_cpu()) {
     post_code(0x30);
     sb_poweron_init();
diff -u -r coreboot-1fe6c64\src\mainboard\asrock\e350m1\romstage.c coreboot-update\src\mainboard\asrock\e350m1\romstage.c
--- coreboot-1fe6c64\src\mainboard\asrock\e350m1\romstage.c	Fri Jul 08 18:51:42 2011
+++ coreboot-update\src\mainboard\asrock\e350m1\romstage.c	Sun Jul 10 00:20:56 2011
@@ -55,21 +55,6 @@
 	// all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
 	__writemsr(0xc0010062, 0);
 
-	if (boot_cpu()) {
-		u8 reg8;
-		// SB800: Program AcpiMmioEn to enable MMIO access to MiscCntrl register
-		outb(0x24, 0xCD6);
-		reg8 = inb(0xCD7);
-		reg8 |= 1;
-		reg8 &= ~(1 << 1);
-		outb(0x24, 0xCD6);
-		outb(reg8, 0xCD7);
-
-		// Program SB800 MiscCntrl
-		*(volatile u32 *)(0xFED80000 + 0xE00 + 0x40) &= ~((1 << 0) | (1 << 2));	/* 48Mhz */
-		*(volatile u32 *)(0xFED80000 + 0xE00 + 0x40) |= 1 << 1;	/* 48Mhz */
-	}
-
 	if (!cpu_init_detectedx && boot_cpu()) {
 		post_code(0x30);
 		sb_poweron_init();
diff -u -r coreboot-1fe6c64\src\southbridge\amd\cimx\sb800\bootblock.c coreboot-update\src\southbridge\amd\cimx\sb800\bootblock.c
--- coreboot-1fe6c64\src\southbridge\amd\cimx\sb800\bootblock.c	Fri Jul 08 18:51:42 2011
+++ coreboot-update\src\southbridge\amd\cimx\sb800\bootblock.c	Sun Jul 10 00:18:13 2011
@@ -85,10 +85,31 @@
 	pci_io_write_config32(dev, 0xa0, save);
 }
 
+static void enable_clocks(void)
+{
+  u8 reg8;
+  u32 reg32;
+  volatile u32 *acpi_mmio = (void *) (0xFED80000 + 0xE00 + 0x40);
+
+  // Program AcpiMmioEn to enable MMIO access to MiscCntrl register
+  outb(0x24, 0xCD6);
+  reg8 = inb(0xCD7);
+  reg8 |= 1;
+  reg8 &= ~(1 << 1);
+  outb(reg8, 0xCD7);
+
+  // Program SB800 MiscCntrl Device_CLK1_sel for 48 MHz (default is 14 MHz)
+  reg32 = *acpi_mmio;
+  reg32 &= ~((1 << 0) | (1 << 2));
+  reg32 |= 1 << 1;
+  *acpi_mmio = reg32;
+}
+
 static void bootblock_southbridge_init(void)
 {
 	/* Setup the rom access for 2M */
 	enable_rom();
 	enable_prefetch();
 	enable_spi_fast_mode();
+	enable_clocks();
 }