> -----Original Message----- > From: [email protected] [mailto:[email protected]] > On Behalf Of xdrudis > Sent: Wednesday, July 13, 2011 12:18 AM > To: Florentin Demetrescu > Cc: [email protected] > Subject: [coreboot] AMD Phenom II 1055T was : Hackaton in Prague 2011 > > On Sat, Jul 09, 2011 at 05:04:43PM +0200, Florentin Demetrescu wrote: > > > > - my objective was to install coreboot on my new board MA785GMT-UDH2. I > had > > bring with me a Phenom II 1055T CPU with 6 cores. Unfortunately I met big > > problems because: > [...] > > coreboot and give it a run, but I will do that ASAP! Also I will > investigate the > > problem of the 6 core Phenom II on this board.. > > > > Isn't it a fam 10 revision E CPU ? > > Coreboot did not have any code specific for Fam 10 rev E last time I > checked (mid feb 2011) (no errata workarounds, no specific > initialization, just a small untested part in fidvid.c). There wasn't > even a constant defined for rev E. > > Back in August 2010 I asked how to extend the revision bitfield that's > used as a trigger for rule based initializations and workarounds, and > in a small thread it was suggested to get rid of it and use a struct, > but I never did. > http://www.coreboot.org/pipermail/coreboot/2010-August/059701.html
AMD Family10 RevE support code was just added into Coreboot a few weeks ago, Please check http://review.coreboot.org/40 in detail, The RevD support code are ready, and will release soon. I think it's not hard to implement RevE, by using the RevD as an reference. thanks -- Kerry > > -- > coreboot mailing list: [email protected] > http://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
