On 8/1/11 1:28 PM, Marc Jones wrote:
Tadas,
On Mon, Aug 1, 2011 at 1:08 PM, Tadas Slotkus<[email protected]> wrote:
Hi, thank you both for the answers. I have studied libpci from
libpayload and removed that device list generation with mallocs. Done a
bunch of trial-error cleanup and now chipset enable and probing for
flash works in ramstage's top of hardwaremain function with this line
included:
x86_setup_mtrrs(36); //from cpu init routine
see attached log: ramstage_with_mtrr.txt.
Also attaching nonworking logs in romstage and ramstage.
Now the question is how these mtrrs should be set in cache_as_ram.inc or
maybe I'm totally wrong? :)
You will need the MTRR setup from CAR. You will want your code to
execute in the XIP area, so that it may be cashed. You may still have
stack/mem issues. That may be the first place you look for problems.
You may need to find a way to optimize for resources.
There will be a problem leaving the XIP area cached while trying to
write to the flash. At the least this means it's not possible to write
the whole flash. Is this intended? What's the plan here?
Stefan
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