Patrick Georgi ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/187
-gerrit commit 7b67759c7f1711e7e7305440bfd476f4f12486bd Author: Wang Qing Pei <[email protected]> Date: Tue Nov 9 09:09:47 2010 +0100 Disable dev3 on ma78gm-us2h Disable bus 0 dev 3 PCI bridge, ma78gm-us2h does not have this slot. Change-Id: Ia355ee385fd0f37793b4bdf1815c033670823eaa Signed-off-by: Wang Qing Pei <[email protected]> Signed-off-by: Patrick Georgi <[email protected]> --- src/mainboard/gigabyte/ma78gm/devicetree.cb | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mainboard/gigabyte/ma78gm/devicetree.cb b/src/mainboard/gigabyte/ma78gm/devicetree.cb index 1aa859f..2fb4824 100644 --- a/src/mainboard/gigabyte/ma78gm/devicetree.cb +++ b/src/mainboard/gigabyte/ma78gm/devicetree.cb @@ -13,7 +13,7 @@ chip northbridge/amd/amdfam10/root_complex device pci 0.0 on end # HT 0x9600 device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 - device pci 3.0 on end # PCIE P2P bridge 0x960b + device pci 3.0 off end # PCIE P2P bridge 0x960b device pci 4.0 on end # PCIE P2P bridge 0x9604 device pci 5.0 off end # PCIE P2P bridge 0x9605 device pci 6.0 off end # PCIE P2P bridge 0x9606 -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
