Patrick Georgi ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/241
-gerrit commit ae3a08acb2fb105e35f218f810619b48f4501f76 Author: Patrick Georgi <[email protected]> Date: Fri Oct 7 14:43:27 2011 +0200 amd/sb600: Enable COM2 at all times in early setup Otherwise with a coreboot log on COM2 (which doesn't work) the boot process takes eons. Change-Id: I886f98b715c1f384c8693f2977671ff15897b5a5 Signed-off-by: Patrick Georgi <[email protected]> --- src/southbridge/amd/sb600/early_setup.c | 9 ++++----- 1 files changed, 4 insertions(+), 5 deletions(-) diff --git a/src/southbridge/amd/sb600/early_setup.c b/src/southbridge/amd/sb600/early_setup.c index 838ea31..5ffd3d8 100644 --- a/src/southbridge/amd/sb600/early_setup.c +++ b/src/southbridge/amd/sb600/early_setup.c @@ -53,11 +53,11 @@ static u8 get_sb600_revision(void) /*************************************** * Legacy devices are mapped to LPC space. -* Serial port 0 +* Serial port 0, 1 * KBC Port * ACPI Micro-controller port * This function does not change port 0x80 decoding. -* Console output through any port besides 0x3f8 is unsupported. +* Console output through any port besides 0x2f8/0x3f8 is unsupported. * If you use FWH ROMs, you have to setup IDSEL. * Reviewed-by: Carl-Daniel Hailfinger * Reviewed against AMD SB600 Register Reference Manual rev. 3.03, section 3.1 @@ -84,10 +84,9 @@ static void sb600_lpc_init(void) pci_write_config32(dev, 0x64, reg32); dev = pci_locate_device(PCI_ID(0x1002, 0x438d), 0); /* LPC Controller */ - /* Decode port 0x3f8-0x3ff (Serial 0) */ - // XXX Serial port decode on LPC is hardcoded to 0x3f8 + /* Decode port 0x3f8-0x3ff (Serial 0), 0x2f8-0x2ff (Serial 1) */ reg8 = pci_read_config8(dev, 0x44); - reg8 |= 1 << 6; + reg8 |= (1 << 6) | (1 << 7); pci_write_config8(dev, 0x44, reg8); /* Decode port 0x60 & 0x64 (PS/2 keyboard) and port 0x62 & 0x66 (ACPI)*/ -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
