Kerry Sheh ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/230
-gerrit commit 35d6eac5744aee2aab1b1b9f35667e67446707c2 Author: Kerry Sheh <[email protected]> Date: Sun Oct 9 14:25:56 2011 +0800 sb800: Update entry point of sb_Before_Pci_Init Formally sb800 cimx entry sb_Before_Pci_Init was called in the device 16.2 enable_dev() function. If the devicetree don't have this device, then sb_Before_Pci_Init will not get called. Change-Id: I76ebad842e90b0f740abbec031165d7c39a80abf Signed-off-by: Kerry Sheh <[email protected]> Signed-off-by: Kerry Sheh <[email protected]> --- src/northbridge/amd/agesa/family10/northbridge.c | 6 ++++++ src/northbridge/amd/agesa/family14/northbridge.c | 3 +++ src/northbridge/amd/amdfam10/northbridge.c | 3 +++ src/southbridge/amd/cimx/sb800/late.c | 3 --- 4 files changed, 12 insertions(+), 3 deletions(-) diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index b3e4c63..b347469 100755 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -38,6 +38,9 @@ #include <Porting.h> #include <AGESA.h> #include <Options.h> +#if CONFIG_AMD_SB_CIMX +#include <sb_cimx.h> +#endif #include "root_complex/chip.h" #include "northbridge.h" #include "amdfam10.h" @@ -775,6 +778,9 @@ static void amdfam10_domain_read_resources(device_t dev) { unsigned reg; +#if CONFIG_AMD_SB_CIMX + sb_Before_Pci_Init(); +#endif /* Find the already assigned resource pairs */ get_fx_devs(); for (reg = 0x80; reg <= 0xd8; reg+= 0x08) { diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index b2ca256..712145b 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -488,6 +488,9 @@ static void domain_read_resources(device_t dev) unsigned reg; printk(BIOS_DEBUG, "\nFam14h - domain_read_resources.\n"); +#if CONFIG_AMD_SB_CIMX + sb_Before_Pci_Init(); +#endif /* Find the already assigned resource pairs */ get_fx_devs(); diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 89bd673..33843b8 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -634,6 +634,9 @@ static void amdfam10_domain_read_resources(device_t dev) { unsigned reg; +#if CONFIG_AMD_SB_CIMX + sb_Before_Pci_Init(); +#endif /* Find the already assigned resource pairs */ get_fx_devs(); for(reg = 0x80; reg <= 0xd8; reg+= 0x08) { diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index b581212..d0e752f 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -418,9 +418,6 @@ static void sb800_enable(device_t dev) break; case (0x16 << 3) | 2: /* 0:16:2 EHCI-USB3 */ sb_config->USBMODE.UsbMode.Ehci3 = dev->enabled; - - /* the last sb800 device */ - sb_Before_Pci_Init(); break; default: -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
