Kyösti Mälkki ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/294
-gerrit commit d3cb685e0112b6cf9430255ea7424e1f8d2ff8dc Author: Kyösti Mälkki <[email protected]> Date: Tue Oct 18 14:32:10 2011 +0300 Add test pattern to assist in DIMM configuration. This is developer's tool. Output from this "rotate ones" -style pattern helps figure out how DIMM addresses are encoded or routed on a certain mainboard. Change-Id: I533a7a873bcc434f99e7faed9dc9337d9ab64196 Signed-off-by: Kyösti Mälkki <[email protected]> --- src/lib/ramtest.c | 72 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 72 insertions(+), 0 deletions(-) diff --git a/src/lib/ramtest.c b/src/lib/ramtest.c index 3f4657f..5bd0223 100644 --- a/src/lib/ramtest.c +++ b/src/lib/ramtest.c @@ -47,6 +47,77 @@ static void phys_memory_barrier(void) #endif } +/** + * Simple rotate ones test pattern for 128bit wide memory bus. + * See console debug output for any dislocated bytes. + * + * for (i=0; i<8; i++) + * for (j=0; j<16; j++) + * *(start + i<<4 + j) = 1<<i; + * + * @start System memory offset, aligned to 128bytes + */ +static void ram_bitset(unsigned long start) +{ + unsigned long value, value2; + unsigned long addr; + uint8_t i; + uint8_t verbose = 0; + /* + * Fill. + */ +#if CONFIG_CACHE_AS_RAM + printk(BIOS_DEBUG, "DRAM bitset write: 0x%08lx\n", start); +#else + print_debug("DRAM bitset write: 0x"); + print_debug_hex32(start); + print_debug("\n"); +#endif + value = 0x01010101; + for(addr = start; addr < (start + 0x80) ; addr += 4) { + + if ((addr & 0xf0) && (! (addr & 0x0f))) + value <<= 1; + write_phys(addr, value); + }; + phys_memory_barrier(); +#if CONFIG_CACHE_AS_RAM + printk(BIOS_DEBUG, "DRAM bitset verify: 0x%08lx\n", start); +#else + print_debug("DRAM bitset verify: 0x"); + print_debug_hex32(start); + print_debug("\n"); +#endif + value = 0x01010101; + for(addr = start; addr < (start + 0x80) ; addr += 4) { + + if ((addr & 0xf0) && (! (addr & 0x0f))) + value <<= 1; + + value2 = read_phys(addr); + i = (value2 != value); + + if ( i || verbose ) { +#if CONFIG_CACHE_AS_RAM + printk(BIOS_ERR, "0x%08lx wr: 0x%08lx rd: 0x%08lx\n", + addr, value, value2); +#else + print_err_hex32(addr); + print_err(" wr: 0x"); + print_err_hex32(value); + print_err(" rd: 0x"); + print_err_hex32(value2); +#endif + } + if (i) + print_err(" FAIL\n"); + else if (verbose) + print_err("\n"); + }; + +} + + static void ram_fill(unsigned long start, unsigned long stop) { unsigned long addr; @@ -174,6 +245,7 @@ void ram_check(unsigned long start, unsigned long stop) print_debug_hex32(stop); print_debug("\n"); #endif + ram_bitset(start); ram_fill(start, stop); /* Make sure we don't read before we wrote */ phys_memory_barrier(); -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
