Hi all,
If setpci -s 14.3 40.b gives back bit7 set, then following patch might detect
the IMC SIO interface. IMC is the embedded 8051 CPU inside SB750/SB820 (or later).
I have also a patch how to embed the firmware to the coreboot image and make it
active. It might be used for Advanced clock calibration or IRDA interface.
Not sure if AMD will/want release some documentation of the programming
interface (for the 8051). I did some advances and partially figured out the
register map of the 8051 part of the interface.
I have also a sample program to communicate with EC firmware through mailbox.
Please let me know if this patch works for you.
Thanks
Rudolf
diff --git a/util/superiotool/Makefile b/util/superiotool/Makefile
index 6f3cfa3..5cc7650 100644
--- a/util/superiotool/Makefile
+++ b/util/superiotool/Makefile
@@ -57,7 +57,7 @@ CONFIG_PCI = yes
ifeq ($(CONFIG_PCI), yes)
CFLAGS += -DPCI_SUPPORT
LIBS += -lpci
-OBJS += pci.o via.o
+OBJS += pci.o via.o amd.o
endif
all: $(PROGRAM)
diff --git a/util/superiotool/amd.c b/util/superiotool/amd.c
new file mode 100644
index 0000000..9173cae
--- /dev/null
+++ b/util/superiotool/amd.c
@@ -0,0 +1,131 @@
+/*
+ * This file is part of the superiotool project.
+ *
+ * Copyright (C) 2011 Rudolf Marek <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "superiotool.h"
+
+#define DEVICE_ID_REG 0x20
+#define DEVICE_REV_REG 0x21
+
+/* Partially documented in coreboot sources, or in 45482.pdf SB800 RRG
+
+Global Registers
+
+reg 0x2: WO - bit0 soft reset.
+reg 0x7: RW - LDN sel
+reg 0x20: DEVID
+reg 0x21: REVID
+
+The IR device is documented in BDG 45483.pdf
+
+*/
+
+static const struct superio_registers reg_table[] = {
+ {0x00, "SB710", {
+ {NOLDN, NULL,
+ {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x28,0x29,0x2a,
+ 0x2b,0x2c,0x2e, 0x2f, EOT},
+ {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}},
+ {0x3, "EC channel 0",
+ {0x30,0x60,0x61, EOT},
+ {NANA,NANA,NANA,EOT}},
+ {0x5, "Irda",
+ {0x30,0x60,0x61,0x70, EOT},
+ {NANA,NANA,NANA,NANA,EOT}},
+ {0x7, "Keyboard Controller",
+ {0x30, EOT},
+ {NANA,EOT}},
+ {0x9, "Mailbox",
+ {0x30,0x60,0x61,0x70,EOT},
+ {NANA,NANA,NANA,NANA,EOT}},
+ {EOT}}},
+ {EOT}
+};
+
+/* same as serverengines */
+static void enter_conf_mode_ec(uint16_t port)
+{
+ OUTB(0x5a, port);
+}
+
+static void exit_conf_mode_ec(uint16_t port)
+{
+ OUTB(0xa5, port);
+}
+
+uint16_t detect_ec(void)
+{
+ uint16_t ec_port;
+ struct pci_dev *dev;
+
+ dev = pci_dev_find(0x1002, 0x439d);
+
+ if (!dev) {
+ return 0;
+ }
+
+ /* is EC disabled ? */
+ if (!(pci_read_byte(dev, 0x40) & (1 << 7)))
+ return 0;
+
+ ec_port = pci_read_word(dev, 0xa4);
+
+ if (!(ec_port & 0x1))
+ return 0;
+
+ ec_port &= ~0x1;
+
+ return ec_port;
+}
+
+/* ignores port, gets autodetected */
+void probe_idregs_amd(uint16_t port)
+{
+ uint8_t rev, devid;
+
+ probing_for("AMD", "", port);
+
+ if (!(port = detect_ec()))
+ return;
+
+ enter_conf_mode_ec(port);
+
+ devid = regval(port, DEVICE_ID_REG);
+ rev = regval(port, DEVICE_REV_REG);
+
+ if (superio_unknown(reg_table, devid)) {
+ if (verbose)
+ printf(NOTFOUND "id=0x%04x, rev=0x%02x\n", devid, rev);
+ exit_conf_mode_ec(port);
+ return;
+ }
+
+ printf("Found %s EC SIO interface (id=0x%04x, rev=0x%02x) at 0x%x\n",
+ get_superio_name(reg_table, devid), devid, rev, port);
+ chip_found = 1;
+
+ dump_superio("AMD EC SIO", reg_table, port, devid, LDN_SEL);
+
+ exit_conf_mode_ec(port);
+}
+
+void print_amd_chips(void)
+{
+ print_vendor_chips("AMD", reg_table);
+}
diff --git a/util/superiotool/superiotool.h b/util/superiotool/superiotool.h
index c5affec..f705a58 100644
--- a/util/superiotool/superiotool.h
+++ b/util/superiotool/superiotool.h
@@ -182,6 +182,10 @@ void print_vendor_chips(const char *vendor,
void probe_idregs_ali(uint16_t port);
void print_ali_chips(void);
+/* amd.c */
+void probe_idregs_amd(uint16_t port);
+void print_amd_chips(void);
+
/* serverengines.c */
void probe_idregs_serverengines(uint16_t port);
void print_serverengines_chips(void);
@@ -235,6 +239,8 @@ static const struct {
{probe_idregs_winbond, {0x2e, 0x4e, 0x3f0, 0x370, 0x250, EOT}},
#ifdef PCI_SUPPORT
{probe_idregs_via, {0x3f0, EOT}},
+ /* in fact read the BASE from HW */
+ {probe_idregs_amd, {0xaa, EOT}},
#endif
{probe_idregs_serverengines, {0x2e, EOT}},
};
@@ -252,6 +258,7 @@ static const struct {
{print_winbond_chips},
#ifdef PCI_SUPPORT
{print_via_chips},
+ {print_amd_chips},
#endif
{print_serverengines_chips},
};
--
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