Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/370
-gerrit commit e47de274deb976f8953101d5894910a8bf1956ab Author: Florian Zumbiehl <[email protected]> Date: Tue Nov 1 20:17:12 2011 +0100 Cycle time at CAS Latency (CLX - 2) is at 25 in DDR2 SPD, not at 26 Change-Id: Ic77854130ad43715daa7c0eb462291db48df9f84 Signed-off-by: Florian Zumbiehl <[email protected]> --- src/northbridge/amd/amdk8/raminit_f.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c index 319293b..dc3addb 100644 --- a/src/northbridge/amd/amdk8/raminit_f.c +++ b/src/northbridge/amd/amdk8/raminit_f.c @@ -1446,7 +1446,7 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, struct mem_i 18, /* *Supported CAS Latencies */ 9, /* *Cycle time at highest CAS Latency CL=X */ 23, /* *Cycle time at CAS Latency (CLX - 1) */ - 26, /* *Cycle time at CAS Latency (CLX - 2) */ + 25, /* *Cycle time at CAS Latency (CLX - 2) */ }; u32 dcl, dcm; u8 common_cl; -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
