Hello, Rock > -----Original Message----- > From: Cui Lei [mailto:[email protected]] > Sent: Friday, December 16, 2011 5:04 PM > To: She, Kerry > Cc: [email protected] > Subject: Re: [coreboot] About the boot steps of the coreboot-V4 > > Hi, Kerry > > Thank you for your reply. I find after __protected_start the execution > will go to the fpu_start (in the fpu_enable.inc), then go to the > cache_as_ram. Now I have a new problem, on my mainboard , there are more > than 2minutes delay between __protected_start and __fpu_start, but on > another mainboard(I just change the romsip code in order to run), it is > ok. If I move the fpu_start code to the entry32.inc, the delay will be > after the __fpu_star What platform do you use? Can you provide some information about the mainboard, chipset and rom chip, With more information in detail, Maybe somebody else can assist. thanks > BRs, > Rock. > > > Hello, Rock > > > > You may need to have a look at the crt0.S, > > Take amd/persimmon as an example: > > #include "config.h" > > #include "src/arch/x86/init/prologue.inc" > > #include "src/cpu/x86/32bit/entry32.inc" > > #include "src/cpu/x86/fpu_enable.inc" > > #include "src/cpu/amd/agesa/cache_as_ram.inc" > > #include "mainboard/amd/persimmon/romstage.inc" > > ~ > > > > "build/romstage/crt0.S" > > > > But I think it's better to learn coreboot by playing with it > > on a mainboard than just reading the code. > > thanks > > > >> -----Original Message----- > >> From: [email protected] > > [mailto:coreboot- > >> [email protected]] On Behalf Of Rock Cui > >> Sent: Wednesday, December 07, 2011 1:19 PM > >> To: [email protected] > >> Subject: [coreboot] About the boot steps of the coreboot-V4 > >> > >> Hi all, > >> I'm learnning the coreboot v4 source code. But when I read the file > >> entry32.inc, I don't know where the execution will jmp to after the > >> __protected_start. > >> I need help. > >> > >> BRs, > >> > >> Rock. > >> > >> -- > >> coreboot mailing list: [email protected] > >> http://www.coreboot.org/mailman/listinfo/coreboot > > > >
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