Vikram Narayanan ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/507
-gerrit commit 05634a9703cb7c52a882a67669800e79a5101e99 Author: Vikram Narayanan <[email protected]> Date: Mon Dec 26 23:30:23 2011 +0530 APIC: Fixed reading MSR_FSB_FREQ register According to Intel's manual, bits 0:2 of MSR 0xCDh gives the FSB frequency. But the code had a right shift of 4 which will always give 267 MHz, as the valid bits are shifted to right. Also, fixed the indentations. Change-Id: I6bf93bac1ee9123af78c003f5a0728f8f0801958 Signed-off-by: Vikram Narayanan <[email protected]> --- src/cpu/x86/lapic/apic_timer.c | 31 +++++++++++++++++++++---------- 1 files changed, 21 insertions(+), 10 deletions(-) diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c index 826f5b6..312951a 100644 --- a/src/cpu/x86/lapic/apic_timer.c +++ b/src/cpu/x86/lapic/apic_timer.c @@ -27,9 +27,10 @@ * memory init. */ -#define FSB_CLOCK_STS 0xcd +#define FSB_CLOCK_STS 0xCD +#define FSB_FREQ_MASK 0x07 -static u32 timer_fsb = 200; // default to 200MHz +static u32 timer_fsb = 200; // default to 200MHz void init_timer(void) { @@ -42,16 +43,26 @@ void init_timer(void) lapic_write(LAPIC_TDCR, LAPIC_TDR_DIV_1); /* Set the initial counter to 0xffffffff */ - lapic_write(LAPIC_TMICT, 0xffffffff); + lapic_write(LAPIC_TMICT, ~0UL); /* Set FSB frequency to a reasonable value */ fsb_clock_sts = rdmsr(FSB_CLOCK_STS); - switch ((fsb_clock_sts.lo >> 4) & 0x07) { - case 0: timer_fsb = 266; break; - case 1: timer_fsb = 133; break; - case 2: timer_fsb = 200; break; - case 3: timer_fsb = 166; break; - case 5: timer_fsb = 100; break; + switch (fsb_clock_sts.lo & FSB_FREQ_MASK) { + case 0: + timer_fsb = 266; + break; + case 1: + timer_fsb = 133; + break; + case 2: + timer_fsb = 200; + break; + case 3: + timer_fsb = 166; + break; + case 5: + timer_fsb = 100; + break; } } @@ -63,5 +74,5 @@ void udelay(u32 usecs) start = lapic_read(LAPIC_TMCCT); do { value = lapic_read(LAPIC_TMCCT); - } while((start - value) < ticks); + } while ((start - value) < ticks); } -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
