Jonathan A. Kollasch ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/519
-gerrit commit b21ed1585ff2c6889678c83e66651d83b5e277e3 Author: Jonathan A. Kollasch <[email protected]> Date: Wed Jan 4 19:43:49 2012 -0600 rs780: power down GPPSB SB lane pads in correct PCIe core Change-Id: I059d5b155cae051f31cc2495f8a47d53e01af808 Signed-off-by: Jonathan A. Kollasch <[email protected]> --- src/southbridge/amd/rs780/pcie.c | 10 ++++++++-- 1 files changed, 8 insertions(+), 2 deletions(-) diff --git a/src/southbridge/amd/rs780/pcie.c b/src/southbridge/amd/rs780/pcie.c index 5e2d985..efa2e58 100644 --- a/src/southbridge/amd/rs780/pcie.c +++ b/src/southbridge/amd/rs780/pcie.c @@ -86,15 +86,21 @@ static void PciePowerOffGppPorts(device_t nb_dev, device_t dev, u32 port) Config & (PCIE_DISABLE_HIDE_UNUSED_PORTS + PCIE_GFX_COMPLIANCE))) { } + /* step 3 Power Down Control for Southbridge */ + if (port != 8) + return; + reg = nbpcie_p_read_index(dev, 0xa2); switch ((reg >> 4) & 0x7) { /* get bit 4-6, LC_LINK_WIDTH_RD */ case 1: - nbpcie_ind_write_index(nb_dev, 0x65, 0x0e0e); + set_pcie_enable_bits(nb_dev, 0x65 | PCIE_CORE_INDEX_GPPSB, + 0x0f0f, 0x0e0e); break; case 2: - nbpcie_ind_write_index(nb_dev, 0x65, 0x0c0c); + set_pcie_enable_bits(nb_dev, 0x65 | PCIE_CORE_INDEX_GPPSB, + 0x0f0f, 0x0c0c); break; default: break; -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
