Kerry Sheh ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/545
-gerrit commit de69b11dfedbfef2619f02af2ebb408e063f4d8e Author: Kerry Sheh <[email protected]> Date: Wed Jan 18 16:16:10 2012 +0800 Inagua: devicetree.cb update Add the slots connection comments to devicetree.cb Change-Id: I3ccb2641c8d04a6a3c66ac11a562ba3b0dc0578a Signed-off-by: Kerry Sheh <[email protected]> Signed-off-by: Kerry Sheh <[email protected]> --- src/mainboard/amd/inagua/devicetree.cb | 16 ++++++++-------- 1 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/mainboard/amd/inagua/devicetree.cb b/src/mainboard/amd/inagua/devicetree.cb index 62cf32d..60bb29b 100644 --- a/src/mainboard/amd/inagua/devicetree.cb +++ b/src/mainboard/amd/inagua/devicetree.cb @@ -30,10 +30,10 @@ chip northbridge/amd/agesa/family14/root_complex device pci 0.0 on end # Root Complex device pci 1.0 on end # Internal Graphics P2P bridge, 9802 to 9806 device pci 1.1 on end # Internal Multimedia - device pci 4.0 on end # PCIE P2P bridge 0x9604 - device pci 5.0 off end # PCIE P2P bridge 0x9605 - device pci 6.0 on end # PCIE P2P bridge 0x9606 - device pci 7.0 off end # PCIE P2P bridge 0x9607 + device pci 4.0 on end # PCIE P2P bridge MXM lane 0 + device pci 5.0 off end # PCIE P2P bridge MXM lane 1 + device pci 6.0 on end # PCIE P2P bridge LAN + device pci 7.0 on end # PCIE P2P bridge MINIPCIE SLOT1 device pci 8.0 off end # NB/SB Link P2P bridge end # agesa northbridge @@ -67,10 +67,10 @@ chip northbridge/amd/agesa/family14/root_complex end #LPC device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} device pci 14.5 on end # USB 2 - device pci 15.0 on end # PCIe PortA - device pci 15.1 on end # PCIe PortB - device pci 15.2 on end # PCIe PortC - device pci 15.3 on end # PCIe PortD + device pci 15.0 on end # PCIe PortA Express Card + device pci 15.1 on end # PCIe PortB NEC USB3.0 + device pci 15.2 on end # PCIe PortC MINIPCIE SLOT2 + device pci 15.3 on end # PCIe PortD PCIE X1 SLOT device pci 16.0 on end # OHCI USB3 device pci 16.2 on end # EHCI USB3 register "gpp_configuration" = "4" #1:1:1:1 -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
