Vikram Narayanan ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/572
-gerrit commit 392ad135233600c2cecfd91cebeb9d1fa831efab Author: Vikram Narayanan <[email protected]> Date: Mon Jan 23 01:44:44 2012 +0530 post code: Replaced hard-coded post code with macro Added a macro in the post code list, which replaces hard coded value in cpu/x86/cache/cache.c Change-Id: I27cb27827272584a8a17a41c111e2dc155196a97 Signed-off-by: Vikram Narayanan <[email protected]> --- src/cpu/x86/cache/cache.c | 3 +-- src/include/console/post_codes.h | 7 +++++++ 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/src/cpu/x86/cache/cache.c b/src/cpu/x86/cache/cache.c index a7cba4a..1df9e08 100644 --- a/src/cpu/x86/cache/cache.c +++ b/src/cpu/x86/cache/cache.c @@ -3,8 +3,7 @@ void x86_enable_cache(void) { - post_code(0x60); + post_code(POST_ENABLING_CACHE); printk(BIOS_INFO, "Enabling cache\n"); enable_cache(); } - diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h index a72da69..1d12e5a 100644 --- a/src/include/console/post_codes.h +++ b/src/include/console/post_codes.h @@ -106,6 +106,13 @@ #define POST_CONSOLE_BOOT_MSG 0x40 /** + * \brief Before enabling the cache + * + * Going to enable the cache + */ +#define POST_ENABLING_CACHE 0x60 + +/** * \brief Devices have been enumerated * * Bus scan, and device enumeration has completed. -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
