Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/615
-gerrit
commit 74c0819a95be57196d9f25aebbf9f61aa8114749
Author: Sven Schnelle <sv...@stackframe.org>
Date: Thu Feb 9 21:05:20 2012 +0100
i5000: halt second BSP
If both FSBs on i5000 are equipped with CPU packages, one CPU
from each package is elected as BSP. To prevent races between
both BSPs, hlt the second BSP.
Change-Id: I6bfcb17d34e9f028280acff1694309e37307ec21
Signed-off-by: Sven Schnelle <sv...@stackframe.org>
---
src/northbridge/intel/i5000/Makefile.inc | 1 +
src/northbridge/intel/i5000/halt_second_bsp.S | 29 +++++++++++++++++++++++++
2 files changed, 30 insertions(+), 0 deletions(-)
diff --git a/src/northbridge/intel/i5000/Makefile.inc
b/src/northbridge/intel/i5000/Makefile.inc
index a5623c0..5e75159 100644
--- a/src/northbridge/intel/i5000/Makefile.inc
+++ b/src/northbridge/intel/i5000/Makefile.inc
@@ -19,3 +19,4 @@
driver-y += northbridge.c
romstage-y += raminit.c udelay.c
+cpu_incs += src/northbridge/intel/i5000/halt_second_bsp.S
diff --git a/src/northbridge/intel/i5000/halt_second_bsp.S
b/src/northbridge/intel/i5000/halt_second_bsp.S
new file mode 100644
index 0000000..a1a1b15
--- /dev/null
+++ b/src/northbridge/intel/i5000/halt_second_bsp.S
@@ -0,0 +1,29 @@
+ /* Save BIST result */
+
+ movl %eax, %ebp
+
+ /* Read the semaphore register of i5000 (BOFL0).
+ If it returns zero, it means there was already
+ another read by another CPU */
+
+ movl $0x800080c0, %eax
+ movw $0xcf8, %dx
+ outl %eax, %dx
+
+ addw $4, %dx
+ inl %dx, %eax
+ cmp $0, %eax
+ jne 1f
+
+ /* degrade BSP to AP */
+ mov $0x1b, %ecx
+ rdmsr
+ andl $(~0x100), %eax
+ wrmsr
+
+ cli
+loop: hlt
+ jmp loop
+
+1: /* Restore BIST */
+ mov %ebp, %eax
--
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