Marc Jones ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/627
-gerrit commit f299de3e00821ddbbe8682c302497228eca968df Author: Marc Jones <[email protected]> Date: Mon Jan 30 19:30:45 2012 -0700 Fix MTRR TOM2 WB cache setup for AMD CPUs > revF. The MTRR check for WB TOM2 setting was only checking revF, not extended family revisions. All families above revf indicate 0xf in the family field and have additional bits in the extended family field. Change-Id: I93d719789acda6b7c42de7fd6d4bad2da866a25f Signed-off-by: Marc Jones <[email protected]> --- src/cpu/amd/mtrr/amd_mtrr.c | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c index c5e01b1..2348b22 100644 --- a/src/cpu/amd/mtrr/amd_mtrr.c +++ b/src/cpu/amd/mtrr/amd_mtrr.c @@ -114,8 +114,9 @@ void amd_setup_mtrrs(void) msr_t msr, sys_cfg; // Test if this CPU is a Fam 0Fh rev. F or later const int cpu_id = cpuid_eax(0x80000001); + printk(BIOS_SPEW, "CPU ID 0x80000001: %x\n", cpu_id); const int has_tom2wb = - (((cpu_id>>8 )&0xf) > 0xf) || // Family > 0F + (((cpu_id>>20 )&0xf) > 0) || // ExtendedFamily > 0 ((((cpu_id>>8 )&0xf) == 0xf) && // Family == 0F (((cpu_id>>16)&0xf) >= 0x4)); // Rev>=F deduced from rev tables if(has_tom2wb) -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
